公开(公告)号：US20230251574A1

公开(公告)日：2023-08-10

申请号：US17890766

申请日：2022-08-18

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Daniel J. FULFORD ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/11 ,  G01B11/16 ,  G03F7/20

CPC classification number: G03F7/11 ,  G01B11/16 ,  G03F7/70783 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a first stress-modification film on the backside surface. The first stress-modification film can be reactive to a first wavelength of light in that exposure to the first wavelength of light modifies an internal stress of the first stress-modification film. The method can further include exposing the first stress-modification film to a pattern of the first wavelength of light to modify the internal stress of the first stress-modification film. The pattern of the first wavelength of light corresponds to the bow measurement.

公开(公告)号：US20230326738A1

公开(公告)日：2023-10-12

申请号：US17967257

申请日：2022-10-17

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Daniel J. FULFORD ,  David C. CONKLIN ,  Anton J. DEVILLIERS

IPC: H01L21/02

CPC classification number: H01L21/02118 ,  H01L21/02318

Abstract: Methods described herein address the chuck degradation challenge that can result in wafer distortion upon wafer coupling, leading to downstream fabrication issues. Techniques include actively monitoring wear of a chuck and counteracting chuck degradation by wafer shape manipulation to maintain an ideal working surface. Techniques include using chuck-based flatness metrology and/or modeling based on previous wafer level results and/or historical database of chuck wear information.

公开(公告)号：US20220238380A1

公开(公告)日：2022-07-28

申请号：US17486189

申请日：2021-09-27

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/822

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. The method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof, and attaching the first side to a carrier substrate. The method can further include forming a composite of a first stress film and a second stress film on a second side of the first semiconductor structure, and separating the carrier substrate from the first semiconductor structure. The method can further include cutting the composite of the first stress film and the second stress film and the first semiconductor structure to define at least one chiplet, and bonding the at least one chiplet to a second semiconductor structure that has a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.

公开(公告)号：US20230326814A1

公开(公告)日：2023-10-12

申请号：US17885038

申请日：2022-08-10

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Andrew WELOTH ,  David C. CONKLIN ,  Anton J. DEVILLIERS

IPC: H01L21/66 ,  H01L21/67 ,  H01L21/68 ,  H01L21/02

CPC classification number: H01L22/34 ,  H01L21/67063 ,  H01L21/0226 ,  H01L21/68 ,  H01L21/67098

Abstract: A device includes a first set of modules configured for wafer shape correction and a second set of modules configured for wafer bonding. The first set of modules includes a metrology module configured to measure wafer shape data of a first wafer and a second wafer, including relative z-height values of the first wafer and the second wafer. A stressor film deposition module is configured to form a first stressor film on the first wafer. A stressor film modification module is configured to modify the first stressor film based on a first modification map that defines adjustments to internal stresses of the first wafer and is generated based on the wafer shape data. The second set of modules includes an alignment module configured to align the first wafer with the second wafer, and a bonding module configured to bond the first wafer to the second wafer.

公开(公告)号：US20230251584A1

公开(公告)日：2023-08-10

申请号：US17889460

申请日：2022-08-17

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD ,  Anton J. DEVILLIERS

IPC: G03F7/20 ,  H01L21/67 ,  H01L21/324 ,  H01L21/66

CPC classification number: G03F7/70783 ,  H01L21/67103 ,  H01L21/67115 ,  H01L21/3247 ,  H01L22/20 ,  H01L21/67288 ,  G03F7/70483

Abstract: Aspects of the present disclosure provide a method for optimizing wafer shape. For example, the method can include receiving a wafer having a working surface for one or more devices to be fabricated thereon and a backside surface opposite to the working surface, measuring the wafer to identify bow measurement of the wafer, and forming a stress-modification film on the backside surface of the wafer. The stress-modification film can be reactive to heat such that applied heat modifies an internal stress of the stress-modification film. The method can also include applying a pattern of heat onto the stress-modification film to modify the internal stress of the stress-modification film, the pattern of heat corresponding to the bow measurement.

公开(公告)号：US20230326767A1

公开(公告)日：2023-10-12

申请号：US17885097

申请日：2022-08-10

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS ,  Andrew WELOTH ,  David C. CONKLIN ,  Anton J. DEVILLIERS

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/67 ,  H01L23/31 ,  H01L21/66

CPC classification number: H01L21/56 ,  H01L24/80 ,  H01L21/67225 ,  H01L21/67109 ,  H01L21/67092 ,  H01L23/3171 ,  H01L22/20 ,  H01L2224/80007 ,  H01L2224/80013 ,  H01L2224/80011 ,  H01L2224/08145 ,  H01L24/08 ,  H01L23/291

Abstract: A method, for bonding a first wafer to a second wafer, includes generating a first modification map based on wafer shape data of the first wafer and the second wafer. The first modification map defines adjustments to internal stresses of the first wafer. A first wafer shape of the first wafer is modified by forming a first stressor film on the first wafer based on the first modification map. The first wafer is aligned with the second wafer after the modifying. The first wafer is bonded to the second wafer.

公开(公告)号：US20230161267A1

公开(公告)日：2023-05-25

申请号：US17888553

申请日：2022-08-16

Applicant: Tokyo Electron Limited

Inventor： Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  Anton J. DEVILLIERS ,  H. Jim FULFORD

IPC: G03F7/20

CPC classification number: G03F7/70633 ,  G03F7/70625

Abstract: Aspects of the present disclosure provide a method for improving overlay alignment of patterning by correcting wafer shape. For example, the method can include receiving a wafer having a working surface with at least partially-fabricated semiconductor devices, and a backside surface opposite to the working surface. The method can also include forming a first stressor film on the backside surface. The first stressor film can modify overlay alignment of the working surface in a first direction across the working surface of the wafer. The method can also include forming one or more first semiconductor structures on the working surface of the wafer. The first semiconductor structures are aligned in the first direction.

公开(公告)号：US20250140614A1

公开(公告)日：2025-05-01

申请号：US18496408

申请日：2023-10-27

Applicant: Tokyo Electron Limited

Inventor： Anthony R. SCHEPIS

IPC: H01L21/66 ,  G01R31/28

Abstract: Aspects of the present disclosure provide a method for creating a product-like surrogate test wafer that mimic a product wafer. For example, the method can include providing a second wafer, forming a stress control layer on the second wafer, and activating the stress control layer according to a first bow measurement of a first wafer to modify an internal stress of the stress control layer such that the second wafer and the stress control layer form a surrogate wafer that has a second bow measurement substantially equal to the first bow measurement.

公开(公告)号：US20230008350A1

公开(公告)日：2023-01-12

申请号：US17684473

申请日：2022-03-02

Applicant: Tokyo Electron Limited

Inventor： Charlotte CUTLER ,  Michael MURPHY ,  Anthony R. SCHEPIS

IPC: H01L21/02

Abstract: Techniques herein include methods for coating a single layer actuator film or multi-layer actuator film on the backside of a wafer. The actuator film includes one or more chemical actuators. Chemical actuators are various molecules, crystals, chemical compounds and other chemical compositions that are capable of imposing directional stress in response to application of an external stimulus on the chemical actuator. The external stimulus can include a particular wavelength of light or polarization of light, or heat (or directed infrared radiation) or load, which can include load-responsive actuation or pressure-responsive actuation.

公开(公告)号：US20220238328A1

公开(公告)日：2022-07-28

申请号：US17473248

申请日：2021-09-13

Applicant: Tokyo Electron Limited

Inventor： Anton J. DEVILLIERS ,  Daniel J. FULFORD ,  Anthony R. SCHEPIS ,  Mark I. GARDNER ,  H. Jim FULFORD

IPC: H01L21/027 ,  H01L23/16

Abstract: Aspects of the present disclosure provide a method for forming a chiplet onto a semiconductor structure. For example, the method can include providing a first semiconductor structure having a first circuit and a first wiring structure formed on a first side thereof. The method can further include attaching the first side of the first semiconductor structure to a carrier substrate. The method can further include forming a stress film on a second side of the first semiconductor structure. The method can further include separating the carrier substrate from the first semiconductor structure. The method can further include cutting the stress film and the first semiconductor structure to define at least one chiplet. The method can further include bonding the at least one chiplet to a second semiconductor structure having a second circuit and a second wiring structure such that the second wiring structure is connected to the first wiring structure.