Invention Application
- Patent Title: FIELD EFFECT TRANSISTOR WITH DISABLED CHANNELS AND METHOD
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Application No.: US17736036Application Date: 2022-05-03
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Publication No.: US20230134741A1Publication Date: 2023-05-04
- Inventor: Yu-Xuan HUANG , Hou-Yu CHEN , Jin CAI , Zhi-Chang LIN , Chih-Hao WANG
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L29/423
- IPC: H01L29/423 ; H01L29/06 ; H01L21/22 ; H01L29/66

Abstract:
A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.
Public/Granted literature
- US12191371B2 Field effect transistor with disabled channels and method Public/Granted day:2025-01-07
Information query
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