公开(公告)号：US20240120273A1

公开(公告)日：2024-04-11

申请号：US18172246

申请日：2023-02-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Jin CAI

IPC: H01L23/522 ,  H10B10/00

CPC classification number: H01L23/5226 ,  H10B10/125

Abstract: A device includes: a first stack of first semiconductor nanostructures; a second stack of second semiconductor nanostructures on the first stack of semiconductor nanostructures; a third stack of first semiconductor nanostructures adjacent the first stack; a first gate structure wrapping around the first stack and the second stack; a second gate structure wrapping around the third stack; a gate isolation structure between the first gate structure and the second gate structure; a dielectric layer on the second gate structure and laterally abutting the gate isolation structure; and a via. The via includes: a first portion that extends in a first direction, the first portion being on the first gate structure, the gate isolation structure and the dielectric layer; and a second portion that extends in a second direction transverse the first direction.

公开(公告)号：US20230039440A1

公开(公告)日：2023-02-09

申请号：US17695605

申请日：2022-03-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Huan JAO ,  Huan-Chieh SU ,  Yi-Bo LIAO ,  Cheng-Chi CHUANG ,  Jin CAI ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/45 ,  H01L29/417 ,  H01L29/40

Abstract: A device includes a substrate. A channel region of a transistor overlies the substrate and a source/drain region is in contact with the channel region. The source/drain region is adjacent to the channel region along a first direction. A source/drain contact is disposed on the source/drain region. A gate electrode is disposed on the channel region and a gate contact is disposed on the gate electrode. A first low-k dielectric layer is disposed between the gate contact and the source/drain contact along the first direction.

公开(公告)号：US20230134741A1

公开(公告)日：2023-05-04

申请号：US17736036

申请日：2022-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Jin CAI ,  Zhi-Chang LIN ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/22 ,  H01L29/66

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

公开(公告)号：US20230037927A1

公开(公告)日：2023-02-09

申请号：US17581789

申请日：2022-01-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ting CHUNG ,  Jin CAI

IPC: H01L29/76 ,  H01L51/00 ,  H01L51/05 ,  H01L29/24 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66

Abstract: An integrated circuit includes a two-dimensional transistor having a channel region having lateral ends in contact with first and second source/drain regions. The transistor includes a gate dielectric that is aligned with the lateral ends of the channel region. The transistor includes a gate metal on the gate dielectric. The gate metal has a relatively small lateral overlap of the first and second source/drain regions.

公开(公告)号：US20250098222A1

公开(公告)日：2025-03-20

申请号：US18961193

申请日：2024-11-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Jin CAI ,  Zhi-Chang LIN ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L21/22 ,  H01L29/06 ,  H01L29/66

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

公开(公告)号：US20210226042A1

公开(公告)日：2021-07-22

申请号：US16746127

申请日：2020-01-17

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Meng-Hsuan HSIAO ,  Tung Ying LEE ,  Wei-Sheng YUN ,  Jin CAI

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762

Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction. Each of the first semiconductor layers at the first portion of the first semiconductor layers have a substantially same thickness.

公开(公告)号：US20240194756A1

公开(公告)日：2024-06-13

申请号：US18311161

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Cheng-Ting CHUNG ,  Jin CAI

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

公开(公告)号：US20220366977A1

公开(公告)日：2022-11-17

申请号：US17876379

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jau-Yi WU ,  Win-San KHWA ,  Jin CAI ,  Yu-Sheng CHEN

IPC: G11C13/00

Abstract: A method includes: generating a first difference between a first resistance value of a first memory cell and a first predetermined resistance value; generating a first signal based on the first difference; applying the first signal to the first memory cell to adjust the first resistance value; and after the first signal is applied to the first memory cell, comparing the first resistance value and the first predetermined resistance value, to further adjust the first resistance value until the first resistance value reaches the first predetermined resistance value. A memory device is also disclosed herein.

公开(公告)号：US20210065792A1

公开(公告)日：2021-03-04

申请号：US17095664

申请日：2020-11-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Jau-Yi WU ,  Win-San KHWA ,  Jin CAI ,  Yu-Sheng CHEN

IPC: G11C13/00

Abstract: A method includes: applying a first signal to memory cells in a memory device, to adjust resistance values of the memory cells; after applying the first signal, applying a second signal to the memory cells other than a first memory cell in the memory cells, to further adjust the resistance values of the memory cells other than the first memory cell. A memory device is also disclosed herein.