公开(公告)号：US20220375931A1

公开(公告)日：2022-11-24

申请号：US17876082

申请日：2022-07-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Pin HUANG ,  Hou-Yu CHEN ,  Chuan-Li CHEN ,  Chih-Kuan YU ,  Yao-Ling HUANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A device comprises a first transistor, a second transistor, a first contact, and a second contact. The first transistor comprises a first gate structure, first source/drain regions on opposite sides of the first gate structure, and first gate spacers spacing the first gate structure apart from the first source/drain regions. The second transistor comprises a second gate structure, second source/drain regions on opposite sides of the second gate structure, and second gate spacers spacing the second gate structure apart from the second source/drain regions. The first contact forms a first contact interface with one of the first source/drain regions. The second contact forms a second contact interface with one of the second source/drain regions. An area ratio of the first contact interface to top surface the first source/drain region is greater than an area ratio of the second contact interface to top surface of the second source/drain region.

公开(公告)号：US20170125413A1

公开(公告)日：2017-05-04

申请号：US15096004

申请日：2016-04-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Sheng WU ,  Chen Hua TSAI ,  Hou-Yu CHEN ,  Chia-Wei SOONG ,  Chih-Pin TSAO

IPC: H01L27/088 ,  H01L29/06 ,  H01L21/265 ,  H01L29/10 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/167

CPC classification number: H01L27/0886 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/167

Abstract: In a method for manufacturing a semiconductor device, a doped layer doped with a first dopant is formed in a substrate. A semiconductor layer is formed on the doped layer. A fin structure is formed by patterning at least the semiconductor layer and the doped layer such that the fin structure comprises a channel region including the semiconductor layer, and a well region including the doped layer. An isolation insulating layer is formed such that the channel region of the fin structure protrudes from the isolation insulating layer and the well region of the fin structure is embedded in the isolation insulating layer. A gate structure is formed over a part of the fin structure and the isolation insulating layer. The semiconductor layer is at least one of a doped silicon layer or a non-doped silicon layer.

公开(公告)号：US20170084741A1

公开(公告)日：2017-03-23

申请号：US14859165

申请日：2015-09-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang LIN ,  Chun-Feng NIEH ,  Huicheng CHANG ,  Hou-Yu CHEN ,  Yong-Yan LU

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7855

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20230134741A1

公开(公告)日：2023-05-04

申请号：US17736036

申请日：2022-05-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Jin CAI ,  Zhi-Chang LIN ,  Chih-Hao WANG

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/22 ,  H01L29/66

Abstract: A device includes a vertical stack of semiconductor nanostructures, a gate structure, a first epitaxial region and a dielectric structure. The gate structure wraps around the semiconductor nanostructures. The first epitaxial region laterally abuts a first semiconductor nanostructure of the semiconductor nanostructures. The dielectric structure laterally abuts a second semiconductor nanostructure of the semiconductor nanostructures and vertically abuts the first epitaxial region.

公开(公告)号：US20210159226A1

公开(公告)日：2021-05-27

申请号：US17170601

申请日：2021-02-08

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yu-Chang LIN ,  Chun-Feng NIEH ,  Huicheng CHANG ,  Hou-Yu CHEN ,  Yong-Yan LU

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/02 ,  H01L27/12 ,  H01L21/84 ,  H01L29/49

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

公开(公告)号：US20210104518A1

公开(公告)日：2021-04-08

申请号：US17105963

申请日：2020-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chung-Pin HUANG ,  Hou-Yu CHEN ,  Chuan-Li CHEN ,  Chih-Kuan YU ,  Yao-Ling HUANG

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

Abstract: A device comprises a first transistor disposed within a first device region of a substrate and a second transistor disposed within a second device region of the substrate. The first transistor comprises first source/drain regions, a first gate structure laterally between the first source/drain regions, and first gate spacers respectively on opposite sidewalls of the first gate structure. The second transistor comprises second source/drain regions, a second gate structure laterally between the second source/drain regions, and second gate spacers respectively on opposite sidewalls of the second gate structure. The second source/drain regions of the second transistor have a maximal width greater than a maximal width of the first source/drain regions of the first transistor, but the second gate spacers of the second transistor have a thickness less than a thickness of the first gate spacers.

公开(公告)号：US20240194756A1

公开(公告)日：2024-06-13

申请号：US18311161

申请日：2023-05-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Xuan HUANG ,  Hou-Yu CHEN ,  Cheng-Ting CHUNG ,  Jin CAI

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: A method for forming vertical gate all around transistors includes forming stack of semiconductor layers on a lower source/drain region. The stack of semiconductor layers includes a first layer, a second layer on the first layer, and a third layer on the second layer. The first and third layers have substantially identical compositions and are selectively etchable with respect to the second layer. The first and second layers can be selectively removed and replaced with inner spacers. The second layer can be selectively removed and replaced with a gate electrode.

公开(公告)号：US20230052295A1

公开(公告)日：2023-02-16

申请号：US17580532

申请日：2022-01-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo LIAO ,  Yu-Xuan HUANG ,  Cheng-Ting CHUNG ,  Hou-Yu CHEN

IPC: H01L29/06 ,  H01L29/66

Abstract: A device includes a substrate, a gate structure, a capping layer, a source/drain region, a source/drain contact, and an air spacer. The gate structure wraps around at least one vertical stack of nanostructure channels over the substrate. The capping layer is on the gate structure. The source/drain region abuts the gate structure. The source/drain contact is on the source/drain region. The air spacer is between the capping layer and the source/drain contact.

公开(公告)号：US20220246522A1

公开(公告)日：2022-08-04

申请号：US17723116

申请日：2022-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Wei Ju LEE ,  Cheng-Ting CHUNG ,  Hou-Yu CHEN ,  Chun-Fu CHENG ,  Kuan-Lun CHENG

IPC: H01L23/522 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/78

Abstract: The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a first vertical structure and a second vertical structure formed over the substrate, and a conductive rail structure between the first and second vertical structures. A top surface of the conductive rail structure can be substantially coplanar with top surfaces of the first and the second vertical structures.

公开(公告)号：US20200227570A1

公开(公告)日：2020-07-16

申请号：US16837051

申请日：2020-04-01

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Hou-Yu CHEN ,  Chao-Ching CHENG ,  Tzu-Chiang CHEN ,  Yu-Lin YANG ,  I-Sheng CHEN

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an isolation layer formed over a substrate, and a plurality of nanostructures formed over the isolation layer. The semiconductor device structure includes a gate structure wrapped around the nanostructures, and an S/D structure wrapped around the nanostructures. The semiconductor device structure includes a first oxide layer between the substrate and the S/D structure. The first oxide layer and the isolation layer are made of different materials. The first oxide layer is in direct contact with the isolation layer.