Invention Publication
- Patent Title: MICROELECTRONICS PACKAGE COMPRISING A PACKAGE-ON-PACKAGE (POP) ARCHITECTURE WITH INKJET BARRIER MATERIAL FOR CONTROLLING BONDLINE THICKNESS AND POP ADHESIVE KEEP OUT ZONE
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Application No.: US18372542Application Date: 2023-09-25
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Publication No.: US20240014097A1Publication Date: 2024-01-11
- Inventor: Elizabeth NOFEN , Shripad GOKHALE , Nick ROSS , Amram EITAN , Nisha ANANTHAKRISHNAN , Robert M. NICKERSON , Purushotham Kaushik MUTHUR SRINATH , Yang GUO , John C. DECKER , Hsin-Yu LI
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H01L23/373
- IPC: H01L23/373 ; H01L21/56 ; H01L23/48 ; H01L21/02 ; H01L21/768

Abstract:
Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.
Information query
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