公开(公告)号：US20210066155A1

公开(公告)日：2021-03-04

申请号：US16557784

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240321807A1

公开(公告)日：2024-09-26

申请号：US18123838

申请日：2023-03-20

Applicant: Intel Corporation

Inventor： Jonas CROISSANT ,  Xavier F. BRUN ,  Gustavo BELTRAN ,  Roberto SERNA ,  Ye Seul NAM ,  Timothy GOSSELIN ,  Jesus S. NIETO PESCADOR ,  Dingying David XU ,  John C. DECKER ,  Ifeanyi OKAFOR ,  Yiqun BAI

IPC: H01L23/00 ,  H01L25/16

CPC classification number: H01L24/32 ,  H01L25/167 ,  H01L24/16 ,  H01L24/73 ,  H01L2224/16145 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/73204

Abstract: Embodiments disclosed herein include multi-die modules. In an embodiment, the multi-die module comprises a first die and a second die coupled to the first die. In an embodiment, the second die comprises a keep out zone that at least partially overlaps the first die. The multi-die module may further comprise an underfill between the first die and the second die. In an embodiment, the underfill is entirely outside the keep out zone, and an edge of the underfill facing the keep out zone is non-vertical.

公开(公告)号：US20240014097A1

公开(公告)日：2024-01-11

申请号：US18372542

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/373 ,  H01L21/565 ,  H01L23/481 ,  H01L21/02288 ,  H01L21/76816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240128152A1

公开(公告)日：2024-04-18

申请号：US18399205

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/02288 ,  H01L21/565 ,  H01L21/76816 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240021493A1

公开(公告)日：2024-01-18

申请号：US18374587

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/76816 ,  H01L21/565 ,  H01L21/02288 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.