公开(公告)号：US20240014097A1

公开(公告)日：2024-01-11

申请号：US18372542

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/373 ,  H01L21/565 ,  H01L23/481 ,  H01L21/02288 ,  H01L21/76816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20210066155A1

公开(公告)日：2021-03-04

申请号：US16557784

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20160093540A1

公开(公告)日：2016-03-31

申请号：US14499120

申请日：2014-09-27

Applicant: INTEL CORPORATION

Inventor： Shuhong LIU ,  Nilanjan Z. GHOSH ,  Zhiyong WANG ,  Deepak GOYAL ,  Shripad GOKHALE ,  Jieping ZHANG

IPC: H01L21/66 ,  H01L21/56 ,  H01L21/78 ,  G01B11/06

CPC classification number: H01L22/12 ,  G01B11/06 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/97 ,  H01L2224/16227 ,  H01L2224/97 ,  H01L2924/15331 ,  H01L2924/1815 ,  H01L2924/37001 ,  H01L2224/81

Abstract: A method including emitting a terahertz beam from a light source at a layer of molding material; detecting a reflectance of the beam; and determining a thickness of the layer of molding material. A system including a panel supporter operable to support a panel including a plurality of substrates arranged in a planar array; a light source operable to emit a terahertz beam at a panel on the panel supporter; a detector operable to detect a reflection of a terahertz beam emitted at a panel; and a processor operable to determine a thickness of a material on the panel based on a time delay for an emitted terahertz beam to be detected by the detector.

Abstract translation: 一种包括在成型材料层从光源发射太赫兹光束的方法; 检测光束的反射率; 并确定成型材料层的厚度。 一种包括面板支撑件的系统，其可操作以支撑包括布置在平面阵列中的多个基板的面板; 光源，其可操作以在所述面板支撑件上的面板处发射太赫兹光束; 检测器，用于检测在面板上发射的太赫兹波束的反射; 以及处理器，其可操作以基于由检测器检测的发射的太赫兹光束的时间延迟来确定面板上的材料的厚度。

公开(公告)号：US20250112136A1

公开(公告)日：2025-04-03

申请号：US18374937

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Jesse JONES ,  Zhixin XIE ,  Bai NIE ,  Shaojiang CHEN ,  Joshua STACEY ,  Mitchell PAGE ,  Brandon C. MARIN ,  Jeremy D. ECTON ,  Nicholas S. HAEHN ,  Astitva TRIPATHI ,  Yuqin LI ,  Edvin CETEGEN ,  Jason M. GAMBA ,  Jacob VEHONSKY ,  Jianyong MO ,  Makoyi WATSON ,  Shripad GOKHALE ,  Mine KAYA ,  Kartik SRINIVASAN ,  Haobo CHEN ,  Ziyin LIN ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Ryan CARRAZZONE ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Hiroki TANAKA ,  Ashay DANI ,  Praveen SREERAMAGIRI ,  Yi LI ,  Ibrahim EL KHATIB ,  Aaron GARELICK ,  Robin MCREE ,  Hassan AJAMI ,  Yekan WANG ,  Andrew JIMENEZ ,  Jung Kyu HAN ,  Hanyu SONG ,  Yonggang Yong LI ,  Mahdi MOHAMMADIGHALENI ,  Whitney BRYKS ,  Shuqi LAI ,  Jieying KONG ,  Thomas HEATON ,  Dilan SENEVIRATNE ,  Yiqun BAI ,  Bin MU ,  Mohit GUPTA ,  Xiaoying GUO

IPC: H01L23/498 ,  H01L23/15

Abstract: Embodiments disclosed herein include apparatuses with glass core package substrates. In an embodiment, an apparatus comprises a substrate with a first surface and a second surface opposite from the first surface. A sidewall is between the first surface and the second surface, and the substrate comprises a glass layer. In an embodiment, a via is provided through the substrate between the first surface and the second surface, and the via is electrically conductive. In an embodiment, a layer in contact with the sidewall of the substrate surrounds a perimeter of the substrate.

公开(公告)号：US20250112174A1

公开(公告)日：2025-04-03

申请号：US18374618

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Siddarth KUMAR ,  Shripad GOKHALE ,  Edvin CETEGEN ,  Praneeth NAMPALLY ,  Astitva TRIPATHI ,  Sairam AGRAHARAM

IPC: H01L23/00 ,  H01L21/3205

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for forming an annealed shape metal alloy (SMA) on a wafer or a die complex. In embodiments, the annealed SMA, when heated above a transition temperature, may enter an Austenite phase and return to the shape that the wafer or die complex had when it was annealed. In embodiments, this may maintain a shape of a wafer or a die complex during higher temperature processing, for example during reflow, when the package undergoes fabrication. Other embodiments may be described and/or claimed.

公开(公告)号：US20250112164A1

公开(公告)日：2025-04-03

申请号：US18374932

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Bohan SHAN ,  Onur OZKAN ,  Ryan CARRAZZONE ,  Rui ZHANG ,  Haobo CHEN ,  Ziyin LIN ,  Yiqun BAI ,  Kyle ARRINGTON ,  Jose WAIMIN ,  Hongxia FENG ,  Srinivas Venkata Ramanuja PIETAMBARAM ,  Gang DUAN ,  Dingying David XU ,  Bin MU ,  Mohit GUPTA ,  Jeremy D. ECTON ,  Brandon C. MARIN ,  Xiaoying GUO ,  Steve S. CHO ,  Ali LEHAF ,  Venkata Rajesh SARANAM ,  Shripad GOKHALE ,  Kartik SRINIVASAN ,  Edvin CETEGEN ,  Mine KAYA ,  Nicholas S. HAEHN ,  Deniz TURAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/065

Abstract: A device comprises a substrate comprising a plurality of build-up layers and a cavity. A bridge die is located within the cavity and a plurality of cavity side bumps are on one side of the bridge die. A plurality of interconnect pads with variable heights are on one of the build-up layers of the substrate coupled to the plurality of the cavity side bumps to bond the bridge die to the substrate.

公开(公告)号：US20240128253A1

公开(公告)日：2024-04-18

申请号：US18399178

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Denis MYASISHCHEV ,  Andrew V. MAZUR ,  Purushotham Kaushik MUTHUR SRINATH ,  Robert M. NICKERSON ,  Shripad GOKHALE

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/315 ,  H01L25/0657 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06582 ,  H01L2225/06589

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.

公开(公告)号：US20240128152A1

公开(公告)日：2024-04-18

申请号：US18399205

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/02288 ,  H01L21/565 ,  H01L21/76816 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240021493A1

公开(公告)日：2024-01-18

申请号：US18374587

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/76816 ,  H01L21/565 ,  H01L21/02288 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20210066273A1

公开(公告)日：2021-03-04

申请号：US16557771

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Denis MYASISHCHEV ,  Andrew V. MAZUR ,  Purushotham Kaushik MUTHUR SRINATH ,  Robert M. NICKERSON ,  Shripad GOKHALE

IPC: H01L25/18 ,  H01L23/31 ,  H01L25/065

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a mold layer and a die embedded in the mold layer. In an embodiment the electronic package further comprises a solder resist with a first surface over the mold layer and a second surface opposite from the first surface. In an embodiment, the second surface comprises a first cavity into the solder resist.