公开(公告)号：US20210066155A1

公开(公告)日：2021-03-04

申请号：US16557784

申请日：2019-08-30

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L21/768 ,  H01L21/02 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240014097A1

公开(公告)日：2024-01-11

申请号：US18372542

申请日：2023-09-25

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/56 ,  H01L23/48 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/373 ,  H01L21/565 ,  H01L23/481 ,  H01L21/02288 ,  H01L21/76816

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240128152A1

公开(公告)日：2024-04-18

申请号：US18399205

申请日：2023-12-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/02 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/02288 ,  H01L21/565 ,  H01L21/76816 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20240021493A1

公开(公告)日：2024-01-18

申请号：US18374587

申请日：2023-09-28

Applicant: Intel Corporation

Inventor： Elizabeth NOFEN ,  Shripad GOKHALE ,  Nick ROSS ,  Amram EITAN ,  Nisha ANANTHAKRISHNAN ,  Robert M. NICKERSON ,  Purushotham Kaushik MUTHUR SRINATH ,  Yang GUO ,  John C. DECKER ,  Hsin-Yu LI

IPC: H01L23/373 ,  H01L21/768 ,  H01L21/56 ,  H01L21/02 ,  H01L23/48

CPC classification number: H01L23/373 ,  H01L21/76816 ,  H01L21/565 ,  H01L21/02288 ,  H01L23/481

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a first package, wherein the first package comprises, a first package substrate, a first die over the first package substrate, a first mold layer over the first package substrate and around the first die, and a plurality of through mold interconnects (TMIs) through the first mold layer. The electronic package may further comprise a second package electrically coupled the first package by the TMIs, wherein the second package comprises a second package substrate, a second die over the second package substrate, and a solder resist over a surface of the second package substrate opposite from the second die. In an embodiment, the electronic package may also comprise a barrier between the first package and the second package.

公开(公告)号：US20200006169A1

公开(公告)日：2020-01-02

申请号：US16022528

申请日：2018-06-28

Applicant: Intel Corporation

Inventor： William WARREN ,  Taylor GAINES ,  Frederick ATADANA ,  Edvin CETEGEN ,  Vipul MEHTA ,  Hsin-Yu LI ,  Yuying WEI ,  Yang GUO ,  Ren ZHANG

IPC: H01L23/16 ,  H01L23/31

Abstract: A structure including a barrier is described. In embodiments, a micro-electronic component may have a first face and a second face, wherein the second face includes interconnect structures and is opposite the first face. A fill material, such as a capillary underfill material (CUF), may fill a gap between the micro-electronic component and the substrate and substantially surround the interconnect structures. In embodiments, a barrier structure may be located on the surface of the substrate and along a perimeter or outside perimeter of the micro-electronic component, wherein a height of the barrier structure exceeds a height of the fill material in at least a portion of an open region of the substrate to confine the fill material to an area bordered by the barrier structure.