- 专利标题: Gate Drivers for Stacked Transistor Amplifiers
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申请号: US18447207申请日: 2023-08-09
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公开(公告)号: US20240039479A1公开(公告)日: 2024-02-01
- 发明人: Poojan Wagh , Kashish Pal , Robert Mark Englekirk , Tero Tapio Ranta , Keith Bargroff , Simon Edward Willard
- 申请人: pSemi Corporation
- 申请人地址: US CA San Diego
- 专利权人: pSemi Corporation
- 当前专利权人: pSemi Corporation
- 当前专利权人地址: US CA San Diego
- 分案原申请号: US15268275 2016.09.16
- 主分类号: H03F1/02
- IPC分类号: H03F1/02 ; H03F3/193 ; H03F1/22
摘要:
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
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