Invention Publication
- Patent Title: THREE-DIMENSIONAL MEMORY DEVICE INCLUDING LOW-K DRAIN-SELECT-LEVEL ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME
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Application No.: US18386456Application Date: 2023-11-02
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Publication No.: US20240064985A1Publication Date: 2024-02-22
- Inventor: Masanori Tsutsumi , Kazuki Isozumi , Peng Zhang
- Applicant: SANDISK TECHNOLOGIES LLC
- Applicant Address: US TX Addison
- Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee: SANDISK TECHNOLOGIES LLC
- Current Assignee Address: US TX Addison
- Main IPC: H10B43/35
- IPC: H10B43/35 ; H10B41/27 ; H10B41/35 ; H10B43/27

Abstract:
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers overlying the word-line-level electrically conductive layers. An array of memory opening fill structures is located within an array of memory openings vertically extending through the alternating stack. An encapsulated cavity vertically extends through the drain-select-level electrically conductive layers. The array of memory opening fill structures includes two rows of first memory opening fill structures that are arranged along a first horizontal direction. Each of the first memory opening fill structures includes a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the encapsulated cavity.
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