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公开(公告)号：US11972819B2
公开(公告)日：2024-04-30
申请号：US17872148
申请日：2022-07-25
发明人： Jiacen Guo , Peng Zhang , Xiang Yang , Yanli Zhang
CPC分类号： G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/102 , G11C16/24
摘要： In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.
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公开(公告)号：US20210408024A1
公开(公告)日：2021-12-30
申请号：US16916186
申请日：2020-06-30
IPC分类号： H01L27/11556 , G11C5/02 , G11C5/06 , H01L29/06 , H01L27/11582
摘要： A memory device disclosed herein. The memory device comprises: a memory string including a first select transistor, a memory cell transistor, and a second select transistor connected in series; a bit line connected to one end of the first select transistor; a source line connected to one end of the second select transistor; a first select line connected to a gate of the first select transistor; a word line connected to a gate of the memory cell transistor; a second select line connected to a gate of the second select transistor; and a control circuit configured to perform, before a program operation, a pre-charge operation comprising: applying a voltage to the second select line connected to the gate of the second select transistor to cause gate-induced drain leakage from the second select transistor.
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3.发明授权公开(公告)号：US10580504B2
公开(公告)日：2020-03-03
申请号：US16002836
申请日：2018-06-07
发明人： Dengtao Zhao , Peng Zhang , Nan Lu , Deepanshu Dutta
IPC分类号： G11C16/04 , G11C16/34 , G11C16/10 , G11C16/08 , H01L27/11582 , H01L27/1157 , H01L27/11565 , G11C11/56
摘要： Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
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公开(公告)号：US09960180B1
公开(公告)日：2018-05-01
申请号：US15470453
申请日：2017-03-27
发明人： Fei Zhou , Raghuveer Makala , Rahul Sharangpani , Keerti Shukla , Yanli Zhang , Peng Zhang
IPC分类号： H01L27/11582 , H01L23/522 , H01L23/532 , H01L23/528 , H01L29/423 , H01L21/768 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/28282 , H01L21/76898 , H01L23/5226 , H01L23/528 , H01L23/5329 , H01L27/11573 , H01L27/11575
摘要： Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge storage elements can be formed in the memory openings. Inter-level charge leakage in a three-dimensional memory device including a charge trapping layer can be minimized by employing a thin continuous charge trapping material layer within each memory opening. After removal of the sacrificial material layers and formation of backside recesses, discrete charge trapping material portions can be formed by selective growth of a charge trapping material from physically exposed surfaces of each thin continuous charge trapping material layer. The discrete charge trapping material portions can function as primary charge storage regions, and inter-level charge leakage can be minimized by the small thickness of the thin continuous charge trapping material layer.
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公开(公告)号：US11201111B2
公开(公告)日：2021-12-14
申请号：US16697560
申请日：2019-11-27
发明人： Dengtao Zhao , Zhiping Zhang , Peng Zhang , Deepanshu Dutta
IPC分类号： H01L27/11578 , H01L23/522 , H01L23/528 , G11C5/06 , G11C16/16 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11519
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.
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公开(公告)号：US11101288B2
公开(公告)日：2021-08-24
申请号：US16710572
申请日：2019-12-11
发明人： Yanli Zhang , Dong-il Moon , Raghuveer S. Makala , Peng Zhang , Wei Zhao , Ashish Baraskar
IPC分类号： H01L27/11582 , H01L21/28 , H01L23/528 , H01L23/532 , H01L23/522 , H01L21/768 , H01L27/11526 , H01L27/11519 , H01L27/11565 , H01L27/11573 , H01L27/11556
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, and memory stack structures extending through the alternating stack. Each of the memory stack structures contains a memory film and a vertical semiconductor channel. At least one of the electrically conductive layers contains a first conductive material portion having a respective inner sidewall that contacts a respective one of the memory films at a vertical interface, and a second conductive material portion that has a different composition from the first conductive material portion, and contacting the first electrically conductive material portion. The first conductive material portion has a lower work function than the second conductive material portion.
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公开(公告)号：US20210134372A1
公开(公告)日：2021-05-06
申请号：US16676023
申请日：2019-11-06
发明人： Zhiping Zhang , Muhammad Masuduzzaman , Huai-Yuan Tseng , Peng Zhang , Dengtao Zhao , Deepanshu Dutta
摘要： A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.
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公开(公告)号：US20240203511A1
公开(公告)日：2024-06-20
申请号：US18221649
申请日：2023-07-13
发明人： Jiacen Guo , Peng Zhang , Xiang Yang , Yanli Zhang
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/102
摘要： The memory device includes a memory block with memory cells arranged in word lines that are divided into sub-blocks. Control circuitry is configured to program each of the word lines of a selected sub-blocks in a plurality of program loops. During at least one program loop, the control circuitry applies a programming pulse to a selected word line. The control circuitry is also configured to simultaneously apply a verify voltage to the selected word line and a pass voltage to unselected word lines. In a first phase of a multi-phase pre-charge process, the control circuitry reduces the voltages applied to the selected word line and at least one unprogrammed word line to a low voltage. In a second phase that follows the first phase, the control circuitry reduces the voltages applied to all word lines that remained at the pass voltage to the low voltage.
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9.发明公开公开(公告)号：US20240112743A1
公开(公告)日：2024-04-04
申请号：US17956409
申请日：2022-09-29
发明人： Peng Zhang , Yanli Zhang
CPC分类号： G11C16/3459 , G11C16/08 , G11C16/24 , G11C16/28
摘要： An apparatus includes memory cells connected to word lines and disposed in strings each defining a channel and coupled to bit lines and a source line. The memory cells are configured to retain a threshold voltage corresponding to data states. A control means is configured to apply programming pulses followed by verification pulses of program verify voltages associated with the data states to the word lines during a program operation. The control means ramps a selected word line voltage applied to the word lines from one of the program verify voltages to approximately zero while ramping voltages applied to the bit lines and the source line to a high supply voltage during a pre-charge operation. The control means ramps an assist voltage applied to a pre-charge assist portion of the memory apparatus to generate gate-induced drain leakage current in the strings and pre-charge the channel during the pre-charge operation.
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10.发明授权公开(公告)号：US10832785B2
公开(公告)日：2020-11-10
申请号：US16840156
申请日：2020-04-03
发明人： Dengtao Zhao , Peng Zhang , Nan Lu , Deepanshu Dutta
IPC分类号： G11C16/34 , G11C16/12 , G11C11/408 , G11C16/04 , G11C8/08
摘要： Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.
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