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1.发明授权公开(公告)号：US11894298B2
公开(公告)日：2024-02-06
申请号：US17655827
申请日：2022-03-22
发明人： Masanori Tsutsumi , Naohiro Hosoda , Shuichi Hamaguchi , Kazuki Isozumi , Genta Mizuno , Yusuke Mukae , Ryo Nakamura , Yu Ueda
IPC分类号： H01L23/522 , H01L23/532 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H01L23/5226 , H01L23/53223 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
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公开(公告)号：US11758718B2
公开(公告)日：2023-09-12
申请号：US17375476
申请日：2021-07-14
发明人： Yu-Chung Lien , Abhijith Prakash , Keyur Payak , Jiahui Yuan , Huai-Yuan Tseng , Shinsuke Yada , Kazuki Isozumi
CPC分类号： H10B41/27 , G11C5/025 , H01L29/7827 , H10B43/27
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, first memory opening fill structures extending through the alternating stack and including a respective first vertical semiconductor channel having a tubular section and a semi-tubular section, second memory opening fill structures, first bit lines electrically connected to a respective subset of the first drain regions, second bit lines electrically connected to a respective subset of the second drain regions, and an erase voltage application circuit configured to electrically bias the first bit lines at a first bit line erase voltage and the second bit lines at a second bit line erase voltage during an erase operation. The first bit line erase voltage is greater than the second bit line erase voltage.
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公开(公告)号：US11581049B2
公开(公告)日：2023-02-14
申请号：US17335909
申请日：2021-06-01
摘要： Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.
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公开(公告)号：US20220383967A1
公开(公告)日：2022-12-01
申请号：US17335909
申请日：2021-06-01
摘要： Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can casuse a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.
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5.发明公开公开(公告)号：US20240064985A1
公开(公告)日：2024-02-22
申请号：US18386456
申请日：2023-11-02
发明人： Masanori Tsutsumi , Kazuki Isozumi , Peng Zhang
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. The electrically conductive layers include word-line-level electrically conductive layers and drain-select-level electrically conductive layers overlying the word-line-level electrically conductive layers. An array of memory opening fill structures is located within an array of memory openings vertically extending through the alternating stack. An encapsulated cavity vertically extends through the drain-select-level electrically conductive layers. The array of memory opening fill structures includes two rows of first memory opening fill structures that are arranged along a first horizontal direction. Each of the first memory opening fill structures includes a respective planar straight sidewall in contact with a respective portion of a pair of straight sidewalls of the encapsulated cavity.
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公开(公告)号：US11776628B2
公开(公告)日：2023-10-03
申请号：US17350770
申请日：2021-06-17
发明人： Xiang Yang , Kazuki Isozumi , Parth Amin
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3459
摘要： The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.
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公开(公告)号：US20220406378A1
公开(公告)日：2022-12-22
申请号：US17350770
申请日：2021-06-17
发明人： Xiang Yang , Kazuki Isozumi , Parth Amin
摘要： The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.
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8.发明授权公开(公告)号：US11289416B2
公开(公告)日：2022-03-29
申请号：US16695775
申请日：2019-11-26
发明人： Masanori Tsutsumi , Naohiro Hosoda , Shuichi Hamaguchi , Kazuki Isozumi , Genta Mizuno , Yusuke Mukae , Ryo Nakamura , Yu Ueda
IPC分类号： H01L29/76 , H01L23/522 , H01L23/532 , H01L27/11519 , H01L27/11582 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11524
摘要： A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.
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