A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.