公开(公告)号：US20240072115A1

公开(公告)日：2024-02-29

申请号：US18168504

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Xiang You ,  Wei-De Ho ,  Hsin Yang Hung ,  Meng-Yu Lin ,  Hsiang-Hung Huang ,  Chun-Fu Cheng ,  Kuan-Kan Hu ,  Szu-Hua Chen ,  Ting-Yun Wu ,  Wei-Cheng Tzeng ,  Wei-Cheng Lin ,  Cheng-Yin Wang ,  Jui-Chien Huang ,  Szuya Liao

IPC: H01L29/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/5283 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.

公开(公告)号：US12131954B1

公开(公告)日：2024-10-29

申请号：US18531047

申请日：2023-12-06

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Che Chi Shih ,  Hsin Yang Hung ,  Ku-Feng Yang ,  Wei-Yen Woon ,  Szuya Liao

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L21/823814 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/456 ,  H01L29/775 ,  H01L29/78696

Abstract: A method includes forming Complementary Field-Effect Transistors including a lower transistor comprising a lower source/drain region, and an upper transistor including an upper source/drain region. An upper dielectric layer over the upper source/drain region and a lower dielectric layer under the upper source/drain region are etched to form an opening. A sidewall of the upper source/drain region and a top surface of the lower source/drain region are exposed to the opening. An epitaxy process is performed to form a first semiconductor layer on the sidewall of the upper source/drain region, and a second semiconductor layer on the top surface of the lower source/drain region. The first semiconductor layer is then removed. A contact plug is formed in the opening to electrically connects the upper source/drain region to the second semiconductor layer and the lower source/drain region.

公开(公告)号：US20240282671A1

公开(公告)日：2024-08-22

申请号：US18327998

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuan Yu Chen ,  Chun-Yen Lin ,  Hsin Yang Hung ,  Ching-Yu Huang ,  Wei-Cheng Lin ,  Jiann-Tyng Tzeng ,  Ting-Yun Wu ,  Wei-De Ho ,  Szuya Liao

IPC: H01L23/48 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L23/481 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/41733 ,  H01L29/66545

Abstract: A method includes forming a multi-layer stack comprising dummy layers and semiconductor layers located alternatingly, and forming a plurality of dummy gate stacks on sidewalls and a top surface of the multi-layer stack. Two of the plurality of dummy gate stacks are immediately neighboring each other, and have a space in between. A first source/drain region and a second source/drain region are formed in the multi-layer stack, with the second source/drain region overlapping the first source/drain region. The method further includes replacing the plurality of dummy gate stacks with a plurality of replacement gate stacks, replacing a first one of the plurality of replacement gate stacks with a first dielectric isolation region, forming a deep contact plug in the space, forming a front-side via over the deep contact plug, and forming a back-side via under the deep contact plug, wherein the front-side via is electrically connected to the back-side via through the deep contact plug.