公开(公告)号：US20240072115A1

公开(公告)日：2024-02-29

申请号：US18168504

申请日：2023-02-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Xiang You ,  Wei-De Ho ,  Hsin Yang Hung ,  Meng-Yu Lin ,  Hsiang-Hung Huang ,  Chun-Fu Cheng ,  Kuan-Kan Hu ,  Szu-Hua Chen ,  Ting-Yun Wu ,  Wei-Cheng Tzeng ,  Wei-Cheng Lin ,  Cheng-Yin Wang ,  Jui-Chien Huang ,  Szuya Liao

IPC: H01L29/06 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/0673 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L23/5283 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78696

Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact. The interconnect structure includes: a conductive layer in contact with the first source/drain contact and the second source/drain contact, the conductive layer being in the gate isolation structure; an opening in the conductive layer, the opening overlapping the fourth source/drain region, the second source/drain region or both; and a dielectric layer in the opening and on the conductive layer in the gate isolation structure.