Invention Application
- Patent Title: GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
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Application No.: US18791963Application Date: 2024-08-01
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Publication No.: US20250028675A1Publication Date: 2025-01-23
- Inventor: JOYDEEP RAY , SELVAKUMAR PANNEER , SAURABH TANGRI , BEN ASHBAUGH , SCOTT JANUS , ABHISHEK APPU , VARGHESE GEORGE , RAVISHANKAR IYER , NILESH JAIN , PATTABHIRAMAN K , ALTUG KOKER , MIKE MACPHERSON , JOSH MASTRONARDE , ELMOUSTAPHA OULD-AHMED-VALL , JAYAKRISHNA P. S , ERIC SAMSON
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: G06F15/78
- IPC: G06F15/78 ; G06F7/544 ; G06F7/575 ; G06F7/58 ; G06F9/30 ; G06F9/38 ; G06F9/50 ; G06F12/02 ; G06F12/06 ; G06F12/0802 ; G06F12/0804 ; G06F12/0811 ; G06F12/0862 ; G06F12/0866 ; G06F12/0871 ; G06F12/0875 ; G06F12/0882 ; G06F12/0888 ; G06F12/0891 ; G06F12/0893 ; G06F12/0895 ; G06F12/0897 ; G06F12/1009 ; G06F12/128 ; G06F15/80 ; G06F17/16 ; G06F17/18 ; G06N3/08 ; G06T1/20 ; G06T1/60 ; G06T15/06 ; H03M7/46

Abstract:
Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.
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