A process for fabricating narrow silicon members from a polycrystalline silicon layer, such as gates for MOS field-effect transistors. The edge of a mask is used to define a gap which exposes a narrow line on the underlying silicon layer. A doped region is formed in the silicon layer through the gap and then the layer is selectively etched. The critical dimensions of the fabricated silicon members are determined by the extent of diffusion of the dopant and are substantially independent of masking tolerances.