发明授权
US4634496A Method for planarizing the surface of an interlayer insulating film in a
semiconductor device
失效
在半导体器件中对层间绝缘膜的表面进行平面化的方法
- 专利标题： Method for planarizing the surface of an interlayer insulating film in a semiconductor device
- 专利标题（中）： 在半导体器件中对层间绝缘膜的表面进行平面化的方法
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申请号： US797986申请日： 1985-11-14
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公开(公告)号： US4634496A公开(公告)日： 1987-01-06
- 发明人: Yasukazu Mase , Masahiro Abe , Masaharu Aoyama
- 申请人： Yasukazu Mase , Masahiro Abe , Masaharu Aoyama
- 申请人地址： JPX Kawasaki
- 专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人： Kabushiki Kaisha Toshiba
- 当前专利权人地址： JPX Kawasaki
- 优先权： JPX59-239560 19841115
- 主分类号： H01L21/3205
- IPC分类号： H01L21/3205 ; H01L21/302 ; H01L21/3065 ; H01L21/3105 ; H01L21/311 ; H01L21/768 ; B44C1/22 ; B29C17/08 ; C03C15/00 ; C03C25/06
摘要：
A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.
公开/授权文献
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