公开(公告)号：US5175115A

公开(公告)日：1992-12-29

申请号：US654488

申请日：1991-02-13

申请人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

发明人： Masahiro Abe ,  Yasukazu Mase ,  Toshihiko Katsura ,  Masaharu Aoyama

IPC分类号： H01L21/48

CPC分类号： H01L21/4846

摘要： Measurement of temperature - internal stress characteristics of an Al thin film formed on an Si substrate is performed. The amount of an impurity or impurities mixed in the thin f ilm can be obtained in accordance with the measured characteristics. A migration start temperature of Al atoms in the thin film in the characteristics obtained when the temperature is increased is fed back as information to the thin film formation step, thereby controlling an impurity amount in an atmosphere for forming the thin film.

摘要翻译： 进行在Si衬底上形成的Al薄膜的温度 - 内部应力特性的测量。 可以根据测量的特性获得混合在薄膜中的杂质或杂质的量。 当温度升高时获得的特性中，薄膜中Al原子的迁移开始温度作为信息反馈到薄膜形成步骤，从而控制用于形成薄膜的气氛中的杂质量。

公开(公告)号：US4634496A

公开(公告)日：1987-01-06

申请号：US797986

申请日：1985-11-14

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L21/3205 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/768 ,  B44C1/22 ,  B29C17/08 ,  C03C15/00 ,  C03C25/06

CPC分类号： H01L21/31116 ,  H01L21/31055 ,  H01L21/76819

摘要： A method for planarizing the surface of an insulation layer deposited on a first interconnection layer to allow a second interconnection layer deposited thereon without causing a breakage of the second interconnection layer. This method is characterized in that at least two insulation films, different in etching characteristics each other, are first formed on the first interconnection layer, and then a resist layer is deposited on the second insulating film. Subsequently, a portion of the resist layer is etched to expose the top surface of the second insulating film, and the second insulating film is selectively and anisotropically etched using the remaining resist layer as a mask. After removing the first insulating film and the remaining resist mark, a third insulating film is deposited to a thickness sufficient to make flat the surface thereof.

摘要翻译： 一种用于平坦化沉积在第一互连层上的绝缘层的表面以允许沉积在其上的第二互连层而不引起第二互连层的破损的方法。 该方法的特征在于，首先在第一互连层上形成至少两个彼此不同的蚀刻特性的绝缘膜，然后在第二绝缘膜上沉积抗蚀剂层。 随后，蚀刻抗蚀剂层的一部分以暴露第二绝缘膜的顶表面，并且使用剩余的抗蚀剂层作为掩模来选择性地和各向异性地蚀刻第二绝缘膜。 在去除第一绝缘膜和剩余的抗蚀剂标记之后，沉积第三绝缘膜至足以使其表面平坦的厚度。

公开(公告)号：US4728627A

公开(公告)日：1988-03-01

申请号：US870117

申请日：1986-06-03

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama

IPC分类号： H01L23/522 ,  H01L21/3205 ,  H01L21/768 ,  H01L27/00 ,  H01L21/28 ,  H01L21/302

CPC分类号： H01L21/76885 ,  H01L21/76877 ,  Y10S438/937

摘要： A method of manufacturing a semiconductor device comprising the steps of preparing a semiconductor substrate on which a first insulation film is formed, forming a first conductive layer on the first insulation film, forming a hillock of the first conductive layer, forming a second insulation film on the structure, removing that portion of the second insulation film, in self-align with the hillock, which is on the hillock, thereby forming a contact hole leading to the first conductive layer, and forming on the structure a second conductive layer extending into the contact hole and contacting the first conductive layer.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤：制备其上形成有第一绝缘膜的半导体衬底，在第一绝缘膜上形成第一导电层，形成第一导电层的小丘，在第一绝缘膜上形成第二绝缘膜 所述结构将所述第二绝缘膜的所述部分与所述小丘上的小丘自对准，从而形成通向所述第一导电层的接触孔，并且在所述结构上形成延伸到所述第一导电层的第二导电层 接触孔并与第一导电层接触。

公开(公告)号：US4613888A

公开(公告)日：1986-09-23

申请号：US634030

申请日：1984-07-24

申请人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

发明人： Yasukazu Mase ,  Masahiro Abe ,  Masaharu Aoyama ,  Takashi Ajima

IPC分类号： H01L21/768 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/316 ,  H01L23/532 ,  H01L21/44 ,  H01L21/47 ,  H01L21/94

CPC分类号： H01L23/5329 ,  H01L2924/0002

摘要： A semiconductor device is disclosed which includes a multilayer formed of a hard inorganic main insulation film and a soft subinsulation film as insulation interlayers, and a hard inorganic insulation film as a final passivation film. The final passivation film is directly deposited on the hard inorganic main insulation film of the multilayer.

摘要翻译： 公开了一种半导体器件，其包括由作为绝缘夹层的硬质无机主绝缘膜和软嵌层膜形成的多层，以及作为最终钝化膜的硬质无机绝缘膜。 最终的钝化膜直接沉积在多层的硬质无机主绝缘膜上。

公开(公告)号：US5103287A

公开(公告)日：1992-04-07

申请号：US605357

申请日：1990-10-30

申请人： Yasukazu Mase ,  Masahiro Abe ,  Toshihiko Katsura

发明人： Yasukazu Mase ,  Masahiro Abe ,  Toshihiko Katsura

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/768 ,  H01L21/8222 ,  H01L23/522 ,  H01L27/06

CPC分类号： H01L21/768 ,  H01L23/5226 ,  H01L2924/0002

摘要： An insulation film is formed on a semiconductor substrate in which semiconductor elements are formed. A plurality of wiring layers and interlaid insulation films are alternately laminated on the insulation film. The design margins of the laminated wiring layers and via holes formed in the interlaid insulation films are set to be larger as they are set at a higher level. The design margin is determined by using the focus margin, mask misalignment due to the mask alignment accuracy, pattern size conversion error, warp of the semiconductor substrate and irregularity of the surface of the semiconductor substrate as parameters.

公开(公告)号：US5100476A

公开(公告)日：1992-03-31

申请号：US499643

申请日：1990-03-27

申请人： Yasukazu Mase ,  Osamu Hirata ,  Masahiro Abe

发明人： Yasukazu Mase ,  Osamu Hirata ,  Masahiro Abe

IPC分类号： B08B3/12 ,  H01L21/00 ,  H01L21/304

CPC分类号： H01L21/67051

摘要： An apparatus for cleaning semiconductor devices has a mixing section for mixing a chemical solution with pure water. A semiconductor substrate to be cleaned is placed on a support. An ultrasonic generator applies ultrasonic vibrations to the supplied pure water. The mixing section mixes a predetermined chemical solution with the pure water applied with the ultrasonic vibrations and supplies a desired pure water solution onto the semiconductor substrate.

公开(公告)号：US5523627A

公开(公告)日：1996-06-04

申请号：US375690

申请日：1995-01-20

申请人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

发明人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

IPC分类号： H01L21/3205 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L23/528

CPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/14

摘要： As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

摘要翻译： 如图所示。 如图4所示，本发明的半导体集成电路器件的布线图形包括从连接孔延伸的布线部分和位于连接孔上的连接部分，并且在所述布线部分侧相对于所述连接孔具有匹配余量， 形成为比预定的宽度大的预定匹配余量，能够确保成功匹配所需的成品率。

公开(公告)号：US5055906A

公开(公告)日：1991-10-08

申请号：US653481

申请日：1991-02-12

申请人： Yasukazu Mase ,  Masahiro Abe ,  Tomie Yamamoto

发明人： Yasukazu Mase ,  Masahiro Abe ,  Tomie Yamamoto

IPC分类号： H01L21/312 ,  H01L21/31 ,  H01L21/314 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC分类号： H01L23/5329 ,  H01L23/5226 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/12044

摘要： A semiconductor device has a first interconnection pattern formed on a semiconductor substrate, and a second interconnection pattern located in and over a through hole formed at a composite insulating layer structure. The composite insulating layer structure is constituted by a first inorganic insulating film and an organic insulating film. At a peripheral region of the second interconnection pattern, the organic insulating film is partially eliminated to form an eliminated portion. The semiconductor device also has a second inorganic insulating film which is formed over the organic insulating film and is directly formed on the first inorganic insulating film, via the eliminated portion.

公开(公告)号：US5044311A

公开(公告)日：1991-09-03

申请号：US431243

申请日：1989-11-03

申请人： Yasukazu Mase ,  Masahiro Abe

发明人： Yasukazu Mase ,  Masahiro Abe

IPC分类号： C23C16/44 ,  C23C16/50 ,  C23C16/509 ,  H01J37/32 ,  H01L21/205 ,  H01L21/31

CPC分类号： H01J37/32477 ,  C23C16/5096 ,  H01J37/32743 ,  H01J2237/3321

摘要： A plasma chemical vapor deposition apparatus comprises a reaction chamber, electrodes provided in the reaction chamber and a side wall constituting part of the reaction chamber and having a wafer access opening, at least the side wall having its surface portion covered with an insulating member. The insulating member prevents abnormal discharge between the electrodes and side wall.

公开(公告)号：USRE37059E1

公开(公告)日：2001-02-20

申请号：US09090401

申请日：1998-06-04

申请人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

发明人： Masahiro Abe ,  Yasukazu Mase ,  Tomie Yamamoto

IPC分类号： G11C1300

CPC分类号： H01L23/528 ,  H01L23/485 ,  H01L23/5226 ,  H01L24/02 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/14

摘要： As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

摘要翻译： 如图所示。 如图4所示，本发明的半导体集成电路器件的布线图形包括从连接孔延伸的布线部分和位于连接孔上的连接部分，并且在所述布线部分侧相对于所述连接孔具有匹配余量， 形成为比预定的宽度大的预定匹配余量，能够确保成功匹配所需的成品率。