发明授权
- 专利标题: Microprocessor having high speed, low noise output buffers
- 专利标题(中): 微处理器具有高速,低噪声输出缓冲器
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申请号: US385656申请日: 1995-02-08
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公开(公告)号: US5502820A公开(公告)日: 1996-03-26
- 发明人: Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
- 申请人: Atsushi Hiraishi , Takashi Akioka , Yutaka Kobayashi , Yuji Yokoyama , Masahiro Iwamura , Tatsumi Yamauchi , Shigeru Takahashi , Hideaki Uchida , Akira Ide
- 申请人地址: JPX Tokyo
- 专利权人: Hitachi, Ltd.
- 当前专利权人: Hitachi, Ltd.
- 当前专利权人地址: JPX Tokyo
- 优先权: JPX1-284731 19891102
- 主分类号: G11C11/417
- IPC分类号: G11C11/417 ; G11C11/409 ; H03K17/16 ; H03K17/687 ; H03K19/003 ; H03K19/0175 ; H03K19/0185 ; H03K19/08 ; H03K19/088 ; H03K19/0944 ; G06F13/00
摘要:
An improved buffer circuit arrangement is provided which is particularly useful for semiconductor integrated circuit semiconductor memories and microprocessors. The buffer circuit is capable of switching large loads in various types of LSIs, and features a low noise and high speed circuit operation. This is accomplished by a parallel connection of output transistors in an output buffer circuit, and by differentiating the starting time of operation between the output transistors connected in parallel without using a delay circuit. For example, differentiating the starting times can be achieved by either providing the transistors with different characteristics from one another or the driving circuits with different characteristics from one another. Another aspect of the circuit is the provision of a two-level preset arrangement which presets the output node of the circuit to predetermined values before the input signals are applied.
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