利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

40 条记录 (耗时 0.028 秒)

    Signal transition detector circuit
    3.
    发明授权
    Signal transition detector circuit 失效
    信号转换检测电路

    公开(公告)号：US5680066A

    公开(公告)日：1997-10-21

    申请号：US182699

    申请日：1994-01-13

    申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira Ide ,  Masahiro Yamamura ,  Hideaki Uchida

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

    摘要： A semiconductor device which includes at least one of (1) an input buffer circuit formed of an input level converter and a non-inverting buffer circuit and an inverting buffer circuit each including BiCMOS circuitry which effects high-speed operation; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device such as for a memory are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

    摘要翻译： 一种半导体器件，其包括以下中的至少一个：（1）由输入电平转换器和非反相缓冲电路构成的输入缓冲电路和各自包括实现高速操作的BiCMOS电路的反相缓冲电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据来自响应于ATD信号的时钟发生器的信号来控制诸如存储器的装置的解码器，读出放大器和输出缓冲器。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US5619151A

    公开(公告)日：1997-04-08

    申请号：US473742

    申请日：1995-06-07

    申请人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira ide ,  Masahiro Yamamura ,  Hideaki Uchida

    发明人： Takashi Akioka ,  Masahiro Iwamura ,  Atsushi Hiraishi ,  Yuji Yokoyama ,  Nozomu Matsuzaki ,  Tatsumi Yamauchi ,  Yutaka Kobayashi ,  Nobuyuki Gotou ,  Akira ide ,  Masahiro Yamamura ,  Hideaki Uchida

    IPC分类号： G11C7/10 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K5/1534 ,  H03K19/0175 ,  H03K5/153 ,  G01R29/02 ,  H03K3/033

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C8/06 ,  G11C8/10 ,  G11C8/18 ,  H03K19/017518 ,  H03K5/1534

    摘要： A semiconductor memory device which includes at least one of (1) an input buffer circuit which generates internal address signals in response to an incoming address; (2) a decoder circuit formed of plural logic gates each of which is composed of the combination of MOS and bipolar circuitry; (3) a sense amplifier circuit including a multiemitter transistor; (4) a signal or address transition detector circuit which includes input circuits each receiving, for example, an address signal of a voltage amplitude and outputting a current amplitude signal in response to a change in level of the address signal, and a detector circuit connected thereto which has a cascode amplifier arranged such that it receives current amplitude signals at an input thereof and in which the cascode amplifier input is maintained at a substantially constant voltage, in which the detection circuit detects a transition of one or more of the current amplitude signals and, in response thereto, generates an ATD signal of a voltage amplitude; and (5) an output buffer circuit, in which the decoder, sense amplifier and output buffer of the device are controlled in accordance with signals from a clock generator, which is responsive to the ATD signal.

    摘要翻译： 一种半导体存储器件，包括以下中的至少一个：（1）响应于输入地址产生内部地址信号的输入缓冲器电路; （2）由多个逻辑门形成的解码器电路，每个逻辑门由MOS和双极电路的组合组成; （3）包括多端子晶体管的读出放大器电路; （4）信号或地址转换检测器电路，其包括各自接收例如电压幅度的地址信号并且响应于地址信号的电平的变化而输出当前振幅信号的输入电路，以及连接的检测器电路 具有共源共栅放大器，其布置成使得其在其输入处接收电流幅度信号，并且其中共源共栅放大器输入保持在基本上恒定的电压，其中检测电路检测到一个或多个当前幅度信号的转变 并且响应于此产生电压幅度的ATD信号; 以及（5）输出缓冲器电路，其中根据响应于ATD信号的时钟发生器的信号来控制器件的解码器，读出放大器和输出缓冲器。

    Semiconductor memory and microprocessor
    5.
    发明授权
    Semiconductor memory and microprocessor 失效
    半导体存储器和微处理器

    公开(公告)号：US5091883A

    公开(公告)日：1992-02-25

    申请号：US552100

    申请日：1990-07-13

    申请人： Nozomu Matsuzaki ,  Takashi Akioka ,  Masahiro Iwamura ,  Atushi Hiraishi ,  Tatsumi Yamauchi ,  Yuji Yokoyama ,  Yutaka Kobayashi ,  Hideaki Uchida

    发明人： Nozomu Matsuzaki ,  Takashi Akioka ,  Masahiro Iwamura ,  Atushi Hiraishi ,  Tatsumi Yamauchi ,  Yuji Yokoyama ,  Yutaka Kobayashi ,  Hideaki Uchida

    IPC分类号： G11C11/41 ,  G11C5/06 ,  G11C11/401 ,  G11C11/409 ,  H01L27/10

    CPC分类号： G11C5/063

    摘要： An input buffer for processing an external signal is provided in one of passways, which is the most closest to a line for equally dividing the whole of a plurality of memory cell blocks longitudinally or laterally into two sections, the passway interposing between the adjacent memory cell blocks of the plurality of memory cell blocks to which a processed signal of the input buffer is transmitted, whereby the length of the signal pass from the input buffer to each memory cell of the memory cell blocks can be shortened. Therefore, since the memory cell or a logic element existing between the input buffer and the memory cell is operated by a pulse of little distortion without delay of time, a access time can be reduced and a processing speed of a microprocessor can be increased. Further, a degree of freedom in designing a system of a memory or the microprocessor is further improved.

    摘要翻译： 用于处理外部信号的输入缓冲器被提供在通路中的一个通道中，该通道最靠近用于将多个存储单元块的整体纵向或横向均匀地分成两部分的通道，该通道插入相邻的存储单元 可以缩短输入缓冲器的经处理信号的多个存储单元块的块，从而可以缩短信号从输入缓冲器传递到存储单元块的每个存储单元的长度。 因此，由于存储单元或者存在于输入缓冲器和存储单元之间的逻辑单元在没有时间延迟的情况下由几个失真的脉冲进行操作，所以可以减少访问时间并且可以提高微处理器的处理速度。 此外，进一步提高了设计存储器或微处理器的系统的自由度。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4868626A

    公开(公告)日：1989-09-19

    申请号：US044202

    申请日：1987-04-30

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L27/0623 ,  Y10S257/903

    摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

    摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

    Semiconductor device
    9.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US4672416A

    公开(公告)日：1987-06-09

    申请号：US843614

    申请日：1986-03-25

    申请人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    发明人： Shinji Nakazato ,  Hideaki Uchida ,  Nobuo Tanba ,  Nobuyuki Gotoo ,  Kazunori Onozawa ,  Atsushi Hiraishi

    IPC分类号： H01L27/082 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/10 ,  H01L29/73 ,  H01L29/732 ,  H01L27/02

    CPC分类号： H01L27/0623 ,  Y10S257/903

    摘要： A semiconductor device facilitates keeping all parasitic resistance values between contact portion of a common source (V.sub.cc) line and intrinsic collector operation regions of respective transistors small enough so as not to exceed predetermined values and so as to be nearly identical. The parasitic resistance values are made small and nearly identical by disposing collector electrode connecting layers between base impurity introducing layers of respective transistors provided with predetermined intervals in a semiconductor substrate. Because of this arrangement to minimize and equalize resistances, the voltage drops generated by the parasitic resistances applied to respective transistors are suppressed so as to be lower than or not substantially exceed the operation threshold voltages of the parasitic transistors.

    摘要翻译： 半导体器件有助于保持公共源极（Vcc）线的接触部分和相应晶体管的本征收集器工作区域之间的所有寄生电阻值足够小以使其不超过预定值并且几乎相同。 通过在半导体衬底中设置有预定间隔的各个晶体管的基底杂质引入层之间设置集电极连接层，使寄生电阻值变得小而几乎相同。 由于这样的结构使电阻最小化和均衡，所以抑制了施加到各个晶体管的寄生电阻产生的电压降，使其低于或基本上不超过寄生晶体管的工作阈值电压。

    Semiconductor integrated circuit device with a protective circuit
    10.
    发明授权
    Semiconductor integrated circuit device with a protective circuit 失效
    具有保护电路的半导体集成电路器件

    公开(公告)号：US4860148A

    公开(公告)日：1989-08-22

    申请号：US37851

    申请日：1987-04-13

    申请人： Masahiro Iwamura ,  Ikuro Masuda ,  Hideaki Uchida

    发明人： Masahiro Iwamura ,  Ikuro Masuda ,  Hideaki Uchida

    IPC分类号： H03K17/00 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H03K17/08 ,  H03K19/003 ,  H03K19/01 ,  H03K19/0948

    CPC分类号： H03K17/08 ,  H01L27/0248

    摘要： A semiconductor integrated circuit device is provided with an input and/or an output terminal and at least one semiconductor device. The circuit has a resistor provided between the input terminal and/or the output terminal and one of the at least one semiconductor devices and an electronic switch connected in parallel with the resistor. The electronic switch is on-off controlled so as to exhibit a relatively low impedance when the semiconductor device is in operation and a relatively high impedance when the semiconductor device is not in operation. Thus, the semiconductor integrated circuit device is operable at a higher speed with an improved reliability and/or with controllable response characteristics, as compared with the conventional device.

    摘要翻译： 半导体集成电路器件设置有输入和/或输出端子和至少一个半导体器件。 电路具有设置在输入端子和/或输出端子之间的电阻器，以及至少一个半导体器件中的一个和与电阻器并联连接的电子开关。 当半导体器件处于工作状态时，电子开关被开关控制，以便表现出相对较低的阻抗，当半导体器件不工作时，电子开关具有较高的阻抗。 因此，与常规器件相比，半导体集成电路器件可以以更高的速度操作，具有改善的可靠性和/或具有可控的响应特性。