Invention Grant
US5583363A Inverter gate circuit of a bi-CMOS structure having common layers
between fets and bipolar transistors
失效
双CMOS结构的逆变器门电路具有在晶体管和双极晶体管之间的公共层
- Patent Title: Inverter gate circuit of a bi-CMOS structure having common layers between fets and bipolar transistors
- Patent Title (中): 双CMOS结构的逆变器门电路具有在晶体管和双极晶体管之间的公共层
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Application No.: US860596Application Date: 1992-03-30
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Publication No.: US5583363APublication Date: 1996-12-10
- Inventor: Hiroshi Momose , Takeo Maeda , Koji Makita
- Applicant: Hiroshi Momose , Takeo Maeda , Koji Makita
- Applicant Address: JPX
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JPX
- Priority: JPX1-20214 19890130
- Main IPC: H01L29/73
- IPC: H01L29/73 ; H01L21/331 ; H01L21/8249 ; H01L27/06 ; H01L27/07 ; H01L29/732 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113
Abstract:
A semiconductor device comprises a p-type semiconductor substrate, an n-type semiconductor well formed on the substrate and connected to a positive power supply, a p-type semiconductor source formed within the n-type semiconductor well, a p-type semiconductor layer formed within the n-type semiconductor well and having a lower impurity concentration than the p-type semiconductor source, a first gate electrode formed over a region between the p-type semiconductor source and the p-type semiconductor layer through an insulating film, an n-type semiconductor emitter formed over the p-type semiconductor layer within the n-type semiconductor well, a first conductive layer formed over the n-type semiconductor well to connect with said p-type semiconductor source.
Public/Granted literature
- US5937606A Securing of reinforcing strips Public/Granted day:1999-08-17
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