公开(公告)号：US5583363A

公开(公告)日：1996-12-10

申请号：US860596

申请日：1992-03-30

申请人： Hiroshi Momose ,  Takeo Maeda ,  Koji Makita

发明人： Hiroshi Momose ,  Takeo Maeda ,  Koji Makita

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/732 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/0716

摘要： A semiconductor device comprises a p-type semiconductor substrate, an n-type semiconductor well formed on the substrate and connected to a positive power supply, a p-type semiconductor source formed within the n-type semiconductor well, a p-type semiconductor layer formed within the n-type semiconductor well and having a lower impurity concentration than the p-type semiconductor source, a first gate electrode formed over a region between the p-type semiconductor source and the p-type semiconductor layer through an insulating film, an n-type semiconductor emitter formed over the p-type semiconductor layer within the n-type semiconductor well, a first conductive layer formed over the n-type semiconductor well to connect with said p-type semiconductor source.

摘要翻译： 半导体器件包括p型半导体衬底，形成在衬底上并连接到正电源的n型半导体阱，形成在n型半导体阱内的p型半导体源，p型半导体层 形成在n型半导体阱内并且具有比p型半导体源低的杂质浓度;通过绝缘膜在p型半导体源和p型半导体层之间的区域上形成的第一栅电极， 在n型半导体阱内的p型半导体层上形成的n型半导体发射体，形成在n型半导体阱上并与所述p型半导体源连接的第一导电层。

公开(公告)号：US5512772A

公开(公告)日：1996-04-30

申请号：US309034

申请日：1994-09-20

申请人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

发明人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/737 ,  H01L27/02 ,  H01L29/161

CPC分类号： H01L27/0623 ,  H01L29/7378

摘要： A semiconductor device of this invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is hetero-bipolar transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

摘要翻译： 本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。 双极晶体管是具有异质结的异双极晶体管。 异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。

公开(公告)号：US5341021A

公开(公告)日：1994-08-23

申请号：US849102

申请日：1992-03-09

申请人： Takeo Maeda ,  Hiroshi Momose

发明人： Takeo Maeda ,  Hiroshi Momose

IPC分类号： H01L27/10 ,  H01L21/331 ,  H01L27/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/73 ,  H01L29/732 ,  H01L29/40 ,  H01L27/082 ,  H01L29/70

CPC分类号： H01L27/0623 ,  H01L29/41708 ,  H01L29/42304

摘要： A contact hole for guiding an emitter electrode of bipolar transistors continuously arrayed and a contact hole for guiding a base electrode are positioned not to be arranged in the continuous array direction of the bipolar transistors. Also, the emitter electrode and the base electrode are respectively drawn from these contact holes in two directions different from the continuous array direction of the bipolar transistors. At least one of the base electrode and the emitter electrode is formed on a conductive layer of a polycide structure contacting an active region in a substrate to be connected.

摘要翻译： 用于引导连续排列的双极晶体管的发射电极的接触孔和用于引导基极的接触孔不被布置在双极晶体管的连续阵列方向上。 此外，发射电极和基极电极分别从与双极晶体管的连续阵列方向不同的两个方向从这些接触孔拉出。 基极和发射电极中的至少一个形成在与要连接的基板中的有源区接触的多晶硅结构的导电层上。

公开(公告)号：US5340751A

公开(公告)日：1994-08-23

申请号：US793540

申请日：1991-11-18

申请人： Takeo Maeda ,  Hiroshi Momose

发明人： Takeo Maeda ,  Hiroshi Momose

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L2/265

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

摘要： A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

摘要翻译： 一种制造半导体器件的方法。 制备半导体衬底，并且在半导体衬底的表面上形成栅极氧化膜。 选择性地去除栅极氧化膜以暴露半导体衬底的部分，并且在所得半导体结构上形成第一多晶硅层。 将杂质注入多晶硅层，并将所得半导体结构退火以活化杂质。 图案化第一多晶硅层以形成双极晶体管的基极和MOS晶体管的栅极和/或漏电极。 然后在所得半导体结构上形成绝缘层。 然后选择性地暴露半导体衬底的部分，并且在所得半导体结构上形成第二多晶硅层。 然后将第二多晶硅层图案化以形成双极晶体管的发射极。

公开(公告)号：US5243557A

公开(公告)日：1993-09-07

申请号：US985109

申请日：1992-12-03

申请人： Takeo Maeda ,  Yukari Unno ,  Hiroshi Momose ,  Masataka Matsui

发明人： Takeo Maeda ,  Yukari Unno ,  Hiroshi Momose ,  Masataka Matsui

IPC分类号： G11C11/413 ,  G11C8/08 ,  G11C11/415 ,  H01L27/10

CPC分类号： G11C8/08

摘要： Disclosed here in is a semiconductor integrated circuit comprising a substrate, a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines, and a plurality of bit lines, and a plurality of word-line drive circuits located near the memory cell array. Each of the word-line drive circuits is a Bi-NMOS circuit which comprises a bipolar transistor for pulling up the potential of the word line and an N-channel MOS transistor for pulling down the potential of the word line. The collector layers of the bipolar transistors are formed of one and the same layer.

摘要翻译： 这里公开的是一种半导体集成电路，包括基板，存储单元阵列，具有排列成行和列的多个存储单元，多个字线和多个位线，以及多个字线驱动电路 位于存储单元阵列附近。 每个字线驱动电路是一个Bi-NMOS电路，它包括用于提高字线电位的双极晶体管和用于下拉字线电位的N沟道MOS晶体管。 双极晶体管的集电极层由同一层形成。

公开(公告)号：US5091322A

公开(公告)日：1992-02-25

申请号：US572136

申请日：1990-08-22

申请人： Takeo Maeda ,  Hiroshi Momose

发明人： Takeo Maeda ,  Hiroshi Momose

IPC分类号： H01L29/73 ,  H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

摘要： A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a gate and/or drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

摘要翻译： 一种制造半导体器件的方法。 制备半导体衬底，并且在半导体衬底的表面上形成栅极氧化膜。 选择性地去除栅极氧化膜以暴露半导体衬底的部分，并且在所得半导体结构上形成第一多晶硅层。 将杂质注入多晶硅层，并将所得半导体结构退火以活化杂质。 图案化第一多晶硅层以形成双极晶体管的基极和MOS晶体管的栅极和/或漏电极。 然后在所得半导体结构上形成绝缘层。 然后选择性地暴露半导体衬底的部分，并且在所得半导体结构上形成第二多晶硅层。 然后将第二多晶硅层图案化以形成双极晶体管的发射极。

公开(公告)号：US5523242A

公开(公告)日：1996-06-04

申请号：US243919

申请日：1994-05-17

申请人： Takeo Maeda ,  Hiroshi Momose

发明人： Takeo Maeda ,  Hiroshi Momose

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/8249 ,  H01L21/265

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

摘要： A method of manufacturing a semiconductor device. A semiconductor substrate is prepared and a gate oxide film is formed on a surface of the semiconductor substrate. The gate oxide film is selectively removed to expose portions of the semiconductor substrate and a first polysilicon layer is formed on a resultant semiconductor structure. Impurities are implanted in the polysilicon layer and a resultant semiconductor structure is annealed to activate the impurities. The first polysilicon layer is patterned to form a base electrode of the bipolar transistor and a source drain electrode of the MOS transistor. An insulating layer is then formed on a resultant semiconductor structure. Portions of the semiconductor substrate are then selectively exposed and a second polysilicon layer is formed on a resultant semiconductor structure. The second polysilicon layer is then patterned to form an emitter electrode of the bipolar transistor.

摘要翻译： 一种制造半导体器件的方法。 制备半导体衬底，并且在半导体衬底的表面上形成栅极氧化膜。 选择性地去除栅极氧化膜以暴露半导体衬底的部分，并且在所得半导体结构上形成第一多晶硅层。 将杂质注入多晶硅层，并将所得半导体结构退火以活化杂质。 图案化第一多晶硅层以形成双极晶体管的基极和MOS晶体管的源极漏极。 然后在所得半导体结构上形成绝缘层。 然后选择性地暴露半导体衬底的部分，并且在所得半导体结构上形成第二多晶硅层。 然后将第二多晶硅层图案化以形成双极晶体管的发射极。

公开(公告)号：US5091760A

公开(公告)日：1992-02-25

申请号：US507037

申请日：1990-04-10

申请人： Takeo Maeda ,  Hiroshi Momose

发明人： Takeo Maeda ,  Hiroshi Momose

IPC分类号： H01L21/285 ,  H01L21/331 ,  H01L21/8249

CPC分类号： H01L29/66272 ,  H01L21/28525 ,  H01L21/8249 ,  Y10S148/009

摘要： A semiconductor device includes a semiconductor substrate, a bipolar transistor and a MOS transistor. The bipolar transistor is formed on the semiconductor substrate and has electrodes. A base electrode of the bipolar transistor and the electrodes of the MOS transistor contain the same kind of impurity so as to form a single layer.

摘要翻译： 半导体器件包括半导体衬底，双极晶体管和MOS晶体管。 双极晶体管形成在半导体衬底上并具有电极。 双极晶体管的基极和MOS晶体管的电极含有相同种类的杂质以形成单层。

公开(公告)号：US5597757A

公开(公告)日：1997-01-28

申请号：US503489

申请日：1995-07-18

申请人： Takeo Maeda ,  Hiroshi Momose

发明人： Takeo Maeda ,  Hiroshi Momose

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/8249 ,  Y10S148/009 ,  Y10S438/978

摘要： An npn bipolar transistor and a p-channel MOS transistor are formed on a p-type silicon substrate. The outer base electrode of the npn bipolar transistor and the gate electrode of the p-channel MOS transistor contain a p-type impurity and are composed of films consisting of the same material. The inner and outer bases are formed in a surface region of the p-type silicon substrate. The outer base is connected to the outer base electrode. The emitter electrode of the npn bipolar transistor is formed on the inner base. A laminated film constituted by a silicon oxide film and a silicon nitride film is formed on a p-type silicon substrate at a position between the outer base electrode and the emitter electrode.

摘要翻译： 在p型硅衬底上形成npn双极晶体管和p沟道MOS晶体管。 npn双极晶体管的外基极和p沟道MOS晶体管的栅电极含有p型杂质，由相同材料构成的膜构成。 内部和外部基底形成在p型硅衬底的表面区域中。 外基座连接到外基极。 npn双极晶体管的发射电极形成在内部基极上。 在外基极和发射极之间的位置，在p型硅衬底上形成由氧化硅膜和氮化硅膜构成的层叠膜。

公开(公告)号：US5399894A

公开(公告)日：1995-03-21

申请号：US23153

申请日：1992-10-28

申请人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

发明人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/737 ,  H01L27/02 ,  H01L29/161

CPC分类号： H01L27/0623 ,  H01L29/7378

摘要： A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

摘要翻译： 本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。 双极晶体管是具有异质结的异质结晶体管。 异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。