公开(公告)号：US08151007B2

公开(公告)日：2012-04-03

申请号：US12078896

申请日：2008-04-08

申请人： Hiroshi Momose

发明人： Hiroshi Momose

IPC分类号： G06F3/00 ,  G06F1/00

CPC分类号： A63F13/42 ,  A63F13/10 ,  A63F13/2145 ,  A63F13/48 ,  A63F13/49 ,  A63F2300/204 ,  A63F2300/301 ,  A63F2300/308 ,  A63F2300/6045 ,  G06F3/0482 ,  G06F3/0486 ,  G06F3/04883 ,  G06F3/04886 ,  G06F13/102

摘要： A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a first memory writing processing to write a first command element having a specific attribute out of the command elements corresponding to the accepted operation in a first memory and a second memory writing processing to write a second command element having an attribute different from the attribute in a second memory, determines whether or not a command element array stored over the first memory and the second memory satisfies an execution allowable condition every execution of the writing processing, and processes information according to the command element array when the satisfaction is determined.

摘要翻译： 信息处理装置的计算机重复接受指定构成命令的多个命令元素中的至少一个的操作，执行第一存储器写入处理中的至少一个以写入具有特定属性的第一命令元素out 对与第一存储器中接受的操作相对应的命令元素和第二存储器写入处理，以在第二存储器中写入具有与该属性不同的属性的第二命令元素来确定存储在第一存储器中的命令元素数组 并且第二存储器在执行写入处理时满足执行允许条件，并且当确定满足时根据命令元素数组处理信息。

公开(公告)号：US20060116203A1

公开(公告)日：2006-06-01

申请号：US11288399

申请日：2005-11-29

申请人： Ryuichi Nakada ,  Hiroshi Momose ,  Takehiko Hosokawa

发明人： Ryuichi Nakada ,  Hiroshi Momose ,  Takehiko Hosokawa

IPC分类号： A63F13/00

CPC分类号： A63F13/426 ,  A63F13/10 ,  A63F13/2145 ,  A63F13/22 ,  A63F13/26 ,  A63F13/92 ,  A63F13/95 ,  A63F2300/1018 ,  A63F2300/1075 ,  A63F2300/301 ,  A63F2300/6045 ,  A63F2300/8005

摘要： A game apparatus includes a display and a touch panel provided thereon. A CPU core displays a game screen on the display. A user draw a circular arc path on the touch panel by continuously touching the touch panel with a stick or the like. In either case of continuous inputs so as to draw a clockwise circular arc path in a right-hander mode or continuous inputs so as to draw a counterclockwise circular arc path in a left-hander mode, it is concluded that the same input operations have been carried out. Accordingly, a user character is moved to the right in proportion to a predetermined angle in the right-hander mode, and the user character is moved to the left in proportion to the predetermined angle in the left-hander mode.

摘要翻译： 游戏装置包括显示器和设置在其上的触摸面板。 CPU核心在显示器上显示游戏画面。 用户通过用棒等连续触摸触摸面板，在触摸面板上绘制圆弧路径。 在连续输入的任何一种情况下，以右手模式或连续输入画出顺时针圆弧路径，以便以左手方式绘制逆时针圆弧路径，得出结论，相同的输入操作已经被 执行。 因此，在右手模式中，以与预定角度成比例的方式将用户角色向右移动，并且在左手模式中用户角色与预定角度成比例地向左移动。

公开(公告)号：US5583363A

公开(公告)日：1996-12-10

申请号：US860596

申请日：1992-03-30

申请人： Hiroshi Momose ,  Takeo Maeda ,  Koji Makita

发明人： Hiroshi Momose ,  Takeo Maeda ,  Koji Makita

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/07 ,  H01L29/732 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/0716

摘要： A semiconductor device comprises a p-type semiconductor substrate, an n-type semiconductor well formed on the substrate and connected to a positive power supply, a p-type semiconductor source formed within the n-type semiconductor well, a p-type semiconductor layer formed within the n-type semiconductor well and having a lower impurity concentration than the p-type semiconductor source, a first gate electrode formed over a region between the p-type semiconductor source and the p-type semiconductor layer through an insulating film, an n-type semiconductor emitter formed over the p-type semiconductor layer within the n-type semiconductor well, a first conductive layer formed over the n-type semiconductor well to connect with said p-type semiconductor source.

摘要翻译： 半导体器件包括p型半导体衬底，形成在衬底上并连接到正电源的n型半导体阱，形成在n型半导体阱内的p型半导体源，p型半导体层 形成在n型半导体阱内并且具有比p型半导体源低的杂质浓度;通过绝缘膜在p型半导体源和p型半导体层之间的区域上形成的第一栅电极， 在n型半导体阱内的p型半导体层上形成的n型半导体发射体，形成在n型半导体阱上并与所述p型半导体源连接的第一导电层。

公开(公告)号：US20150031461A1

公开(公告)日：2015-01-29

申请号：US14261066

申请日：2014-04-24

申请人： HIROSHI MOMOSE ,  KAORI ANDO ,  HIDEAKI ARAKI ,  TAKAYUKI ITO ,  NAYUTA TAGA ,  YOSHIHIRO HATTA

发明人： HIROSHI MOMOSE ,  KAORI ANDO ,  HIDEAKI ARAKI ,  TAKAYUKI ITO ,  NAYUTA TAGA ,  YOSHIHIRO HATTA

IPC分类号： A63F13/60 ,  A63F13/35

CPC分类号： A63F13/327 ,  A63F13/73 ,  A63F13/825 ,  A63F13/95

摘要： An example system includes: a contactless communication part that performs contactless communication with a data storage medium having a contactless communication function; a data writing part that writes data to the data storage medium by the contactless communication part; a storage part that stores the data written by the data writing part; and a corruption determination part that determines whether the data stored in the data storage medium is corrupted or not. When the corruption determination part determines that the data is corrupted, the data writing part writes the data stored in the storage part, to the data storage medium.

摘要翻译： 示例性系统包括：非接触通信部分，其与具有非接触通信功能的数据存储介质执行非接触式通信; 数据写入部，其通过非接触通信部向数据存储介质写入数据; 存储由数据写入部分写入的数据的存储部分; 以及确定存储在数据存储介质中的数据是否已损坏的损坏确定部分。 当损坏确定部分确定数据被破坏时，数据写入部分将存储在存储部分中的数据写入数据存储介质。

公开(公告)号：US08558792B2

公开(公告)日：2013-10-15

申请号：US11304631

申请日：2005-12-16

申请人： Hiroshi Momose

发明人： Hiroshi Momose

IPC分类号： G09G5/08 ,  G06F3/033 ,  G06F17/00 ,  G06F19/00 ,  A63F9/24 ,  A63F13/00

CPC分类号： A63F13/426 ,  A63F13/10 ,  A63F13/2145 ,  A63F13/52 ,  A63F2300/1062 ,  A63F2300/1075 ,  A63F2300/301 ,  A63F2300/66

摘要： The present invention is a storage medium storing a game program to be executed by a computer in a game apparatus comprising an input device for detecting positions designated by a player on an input surface. The game apparatus calculates an input graphic drawn on the input surface by using the positions detected by the input device. The game apparatus further calculates a degree of similarity between a share of each reference pattern indicated by previously stored shape data and a shape of the input graphic. Also, the game apparatus sets a reference value to each of the reference patterns. The game apparatus identifies the shape of the input graphic from among a plurality of reference patterns by using a result obtained by performing a predetermined calculation for each of the plurality of reference patterns through using the degree of similarity and the reference value set to one process is performed in accordance with the identified shape.

摘要翻译： 本发明是一种存储由游戏装置中的计算机执行的游戏程序的存储介质，该游戏装置包括用于检测由输入面上的玩家指定的位置的输入装置。 游戏装置通过使用由输入装置检测的位置来计算在输入面上画出的输入图形。 游戏装置还计算由先前存储的形状数据指示的每个参考图案的份额与输入图形的形状之间的相似度。 此外，游戏装置对每个参考图案设置参考值。 游戏装置通过使用通过使用相似程度对多个参考图案中的每一个执行预定计算而获得的结果，从多个参考图案中识别输入图形的形状，并且对一个处理设置的参考值是 根据识别的形状进行。

公开(公告)号：US20120166678A1

公开(公告)日：2012-06-28

申请号：US13410462

申请日：2012-03-02

申请人： Hiroshi MOMOSE

发明人： Hiroshi MOMOSE

IPC分类号： G06F3/00

CPC分类号： A63F13/42 ,  A63F13/10 ,  A63F13/2145 ,  A63F13/48 ,  A63F13/49 ,  A63F2300/204 ,  A63F2300/301 ,  A63F2300/308 ,  A63F2300/6045 ,  G06F3/0482 ,  G06F3/0486 ,  G06F3/04883 ,  G06F3/04886 ,  G06F13/102

摘要： A computer of an information processing apparatus repeatedly accepts an operation to designate at least one of a plurality of command elements making up of a command, executes at least any one of a first memory writing processing to write a first command element having a specific attribute out of the command elements corresponding to the accepted operation in a first memory and a second memory writing processing to write a second command element having an attribute different from the attribute in a second memory, determines whether or not a command element array stored over the first memory and the second memory satisfies an execution allowable condition every execution of the writing processing, and processes information according to the command element array when the satisfaction is determined.

摘要翻译： 信息处理装置的计算机重复接受指定构成命令的多个命令元素中的至少一个的操作，执行第一存储器写入处理中的至少一个以写入具有特定属性的第一命令元素out 对与第一存储器中接受的操作相对应的命令元素和第二存储器写入处理，以在第二存储器中写入具有与该属性不同的属性的第二命令元素来确定存储在第一存储器中的命令元素数组 并且第二存储器在执行写入处理时满足执行允许条件，并且当确定满足时根据命令元素数组处理信息。

公开(公告)号：US20050270289A1

公开(公告)日：2005-12-08

申请号：US10914112

申请日：2004-08-10

申请人： Hiroshi Momose

发明人： Hiroshi Momose

IPC分类号： A63F13/00 ,  G06T7/00 ,  G06T11/20 ,  G09G5/02

CPC分类号： G06T11/203 ,  A63F2300/1075 ,  A63F2300/301 ,  G06F3/04883 ,  G06K9/222

摘要： An information processing device executing a graphics identification program detects a trace drawn on an input surface as coordinate points in chronological order. Coordinate points for representing the trace are selected from a group of coordinate points arranged in chronological order. Lengths of line segments obtained by connecting the selected coordinate points in chronological order are calculated. Also, for each line segment, an absolute angle and a relative angle are calculated. A trace graph in an orthogonal coordinate system, whose first axis indicates a line segment distance and whose second axis indicates an angle of a line segment whose start point is one of the selected coordinate points, is compared with a reference graphic graph representing a reference graphic in the orthogonal coordinate system, thereby identifying a reference graphic represented by a reference graphic graph which most closely resembles the trace graph as a shape of the trace.

摘要翻译： 执行图形识别程序的信息处理装置以时间顺序检测在输入表面上绘制的轨迹作为坐标点。 从一组以时间顺序排列的坐标点中选择用于表示轨迹的坐标点。 计算通过按时间顺序连接所选坐标点获得的线段长度。 此外，对于每个线段，计算绝对角度和相对角度。 正交坐标系中的轨迹图，其第一轴表示线段距离，其第二轴表示起点是所选择的坐标点之一的线段的角度，与表示参考图形的参考图形进行比较 在正交坐标系中，从而识别由跟踪图形最接近的参考图形表示的参考图形作为轨迹的形状。

公开(公告)号：US5629537A

公开(公告)日：1997-05-13

申请号：US346829

申请日：1994-11-30

申请人： Tetsu Nagamatsu ,  Hiroshi Momose

发明人： Tetsu Nagamatsu ,  Hiroshi Momose

IPC分类号： H01L21/8249 ,  H01L21/82 ,  H01L27/06 ,  H01L27/118 ,  H01L27/10

CPC分类号： H01L27/11896

摘要： A semiconductor device has a plurality of basic cells fabricated on a single semiconductor substrate. Each of the basic cells comprises a first-conduction-type FETs, a second-conduction-type FETs, and a bipolar transistor. The collector region of the bipolar transistor is formed in a well region where the first-conduction-type FETs are formed. The bipolar transistor is formed between the first-conduction-type FETs of adjacent ones of the basic cells separated by an element insulation film.

摘要翻译： 半导体器件具有在单个半导体衬底上制造的多个基本单元。 每个基本单元包括第一导电型FET，第二导电型FET和双极晶体管。 双极晶体管的集电极区域形成在形成第一导电型FET的阱区中。 双极晶体管形成在由元件绝缘膜隔开的相邻基本单元的第一导电型FET之间。

公开(公告)号：US5597757A

公开(公告)日：1997-01-28

申请号：US503489

申请日：1995-07-18

申请人： Takeo Maeda ,  Hiroshi Momose

发明人： Takeo Maeda ,  Hiroshi Momose

IPC分类号： H01L21/8249 ,  H01L27/06 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L21/8249 ,  Y10S148/009 ,  Y10S438/978

摘要： An npn bipolar transistor and a p-channel MOS transistor are formed on a p-type silicon substrate. The outer base electrode of the npn bipolar transistor and the gate electrode of the p-channel MOS transistor contain a p-type impurity and are composed of films consisting of the same material. The inner and outer bases are formed in a surface region of the p-type silicon substrate. The outer base is connected to the outer base electrode. The emitter electrode of the npn bipolar transistor is formed on the inner base. A laminated film constituted by a silicon oxide film and a silicon nitride film is formed on a p-type silicon substrate at a position between the outer base electrode and the emitter electrode.

摘要翻译： 在p型硅衬底上形成npn双极晶体管和p沟道MOS晶体管。 npn双极晶体管的外基极和p沟道MOS晶体管的栅电极含有p型杂质，由相同材料构成的膜构成。 内部和外部基底形成在p型硅衬底的表面区域中。 外基座连接到外基极。 npn双极晶体管的发射电极形成在内部基极上。 在外基极和发射极之间的位置，在p型硅衬底上形成由氧化硅膜和氮化硅膜构成的层叠膜。

公开(公告)号：US5399894A

公开(公告)日：1995-03-21

申请号：US23153

申请日：1992-10-28

申请人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

发明人： Takeo Maeda ,  Hiroshi Momose ,  Yukihiro Urakawa ,  Masataka Matsui

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/165 ,  H01L29/737 ,  H01L27/02 ,  H01L29/161

CPC分类号： H01L27/0623 ,  H01L29/7378

摘要： A semiconductor device of the present invention includes a bipolar transistor and MOS transistors which are formed on the same semiconductor substrate. The bipolar transistor is heterojunction transistor having a hetero junction. The hetero-bipolar transistor is a bipolar transistor of double-hetero structure in which a material used for forming the base region thereof has a band gap narrower than a material used for forming the emitter and collector regions thereof.

摘要翻译： 本发明的半导体器件包括形成在同一半导体衬底上的双极晶体管和MOS晶体管。 双极晶体管是具有异质结的异质结晶体管。 异双极晶体管是双异质结构的双极晶体管，其中用于形成其基极区的材料的带隙比用于形成其发射极和集电极区域的材料窄。