发明授权
US5633830A Random access memory block circuitry for programmable logic array
integrated circuit devices
失效
用于可编程逻辑阵列集成电路器件的随机存取存储器块电路
- 专利标题： Random access memory block circuitry for programmable logic array integrated circuit devices
- 专利标题（中）： 用于可编程逻辑阵列集成电路器件的随机存取存储器块电路
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申请号： US555106申请日： 1995-11-08
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公开(公告)号： US5633830A公开(公告)日： 1997-05-27
- 发明人: Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
- 申请人： Chiakang Sung , Wanli Chang , Joseph Huang , Richard G. Cliff
- 申请人地址： CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： CA San Jose
- 主分类号： G01R31/3185
- IPC分类号： G01R31/3185 ; G11C8/12 ; G11C8/16 ; G11C29/32 ; H03K19/173 ; H03K19/177 ; G11C7/00
摘要：
A relatively large block of random access memory ("RAM") may be provided on a programmable logic array integrated circuit device for use as read-only memory ("ROM") or RAM during operation of the device to perform logic. The RAM block is connected in the circuitry of the device so that it can be programmed and verified compatibly with other memory on the device. Thereafter the circuitry of the RAM block allows it to be switched over to operation as RAM or ROM during logic operation of the device.
公开/授权文献
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