发明授权
US5856697A Integrated dual layer emitter mask and emitter trench for BiCMOS
processes
失效
用于BiCMOS工艺的集成双层发射极掩模和发射极沟槽
- 专利标题： Integrated dual layer emitter mask and emitter trench for BiCMOS processes
- 专利标题（中）： 用于BiCMOS工艺的集成双层发射极掩模和发射极沟槽
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申请号： US895270申请日： 1997-07-14
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公开(公告)号： US5856697A公开(公告)日： 1999-01-05
- 发明人: Stephen Chambers , Brian J. Brown , Chan-Hong Chern , Robert Chau , Leopoldo D. Yau
- 申请人： Stephen Chambers , Brian J. Brown , Chan-Hong Chern , Robert Chau , Leopoldo D. Yau
- 申请人地址： CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： CA Santa Clara
- 主分类号： H01L21/331
- IPC分类号： H01L21/331 ; H01L21/8249 ; H01L29/08 ; H01L29/76 ; H01L29/94 ; H01L31/062 ; H01L31/113
摘要：
A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.
公开/授权文献
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