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    Transistor with low resistance tip and method of fabrication in a CMOS process
    1.
    发明授权
    Transistor with low resistance tip and method of fabrication in a CMOS process 失效
    具有低电阻尖端的晶体管和CMOS工艺中的制造方法

    公开(公告)号：US06165826A

    公开(公告)日：2000-12-26

    申请号：US581243

    申请日：1995-12-29

    申请人： Robert S. Chau ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Leopoldo D. Yau

    发明人： Robert S. Chau ,  Chia-Hong Jan ,  Chan-Hong Chern ,  Leopoldo D. Yau

    IPC分类号： H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/417 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/2254 ,  H01L21/2257 ,  H01L21/2807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66613 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

    摘要： A novel transistor with a low resistance ultra shallow tip region and its method of fabrication in a complementary metal oxide semiconductor (CMOS) process. According to the preferred method of the present invention, a first gate dielectric and a first gate electrode are formed on a first portion of a semiconductor substrate having a first conductivity type, and a second gate dielectric and a said gate electrode are formed on a second portion of semiconductor substrate having a second conductivity type. A silicon nitride layer is formed over the first portion of the semiconductor substrate including the first gate electrode and over the second portion of the semiconductor substrate including the second gate electrode. The silicon nitride layer is removed from the second portion of the silicon substrate and from the top of the second gate electrode to thereby form a first pair of silicon nitride spacers adjacent to opposite sides of the second gate electrode. A pair of recesses are then formed in the second portion of the semiconductor substrate in alignment with the first pair of sidewall spacers. A selectively deposited semiconductor material is then formed in the recesses.

    摘要翻译： 一种具有低电阻超浅尖端区域的新型晶体管及其在互补金属氧化物半导体（CMOS）工艺中制造的方法。 根据本发明的优选方法，在具有第一导电类型的半导体衬底的第一部分上形成第一栅极电介质和第一栅电极，并且在第二栅极电极上形成第二栅极电介质和所述栅电极 具有第二导电类型的半导体衬底的部分。 在包括第一栅电极的半导体衬底的第一部分之上以及包括第二栅电极的半导体衬底的第二部分之上形成氮化硅层。 从硅衬底的第二部分和第二栅电极的顶部去除氮化硅层，从而形成与第二栅电极的相对侧相邻的第一对氮化硅间隔物。 然后在半导体衬底的第二部分中与第一对侧壁间隔件对准地形成一对凹部。 然后在凹部中形成选择性淀积的半导体材料。

    Method and apparatus for conditioning of chemical-mechanical polishing pads
    2.
    发明授权
    Method and apparatus for conditioning of chemical-mechanical polishing pads 失效
    用于调节化学机械抛光垫的方法和装置

    公开(公告)号：US5611943A

    公开(公告)日：1997-03-18

    申请号：US536467

    申请日：1995-09-29

    申请人： Kenneth C. Cadien ,  Leopoldo D. Yau

    发明人： Kenneth C. Cadien ,  Leopoldo D. Yau

    IPC分类号： B24B37/04 ,  B24B29/00

    CPC分类号： B24B37/042 ,  B24B53/017

    摘要： A method and apparatus for conditioning and/or rinsing a pad in a chemical-mechanical polisher. A scoring apparatus is rotated about its center directly over the polishing pad of the chemical-mechanical polisher. The scoring apparatus scores the pad surface while rotating above the pad. Consequently the pad is conditioned in a uniform and concentric fashion.

    摘要翻译： 用于在化学机械抛光机中调节和/或漂洗垫的方法和装置。 刻痕设备围绕其中心旋转直接在化学机械抛光机的抛光垫上。 评分装置在垫上方旋转时评分垫表面。 因此，垫以均匀和同心的方式调节。

    Method of making emitter trench BiCMOS using integrated dual layer emitter mask
    3.
    发明授权
    Method of making emitter trench BiCMOS using integrated dual layer emitter mask 失效
    使用集成双层发射器掩模制造发射极沟槽BiCMOS的方法

    公开(公告)号：US5488003A

    公开(公告)日：1996-01-30

    申请号：US40673

    申请日：1993-03-31

    申请人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    发明人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L21/265

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

    摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

    摘要翻译： 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。

    Process for forming a thin oxide layer
    4.
    发明授权
    Process for forming a thin oxide layer 失效
    用于形成薄氧化物层的方法

    公开(公告)号：US5244843A

    公开(公告)日：1993-09-14

    申请号：US809971

    申请日：1991-12-17

    申请人： Robert S. K. Chau ,  William L. Hargrove ,  Leopoldo D. Yau

    发明人： Robert S. K. Chau ,  William L. Hargrove ,  Leopoldo D. Yau

    IPC分类号： H01L21/28 ,  H01L21/31 ,  H01L21/316 ,  H01L21/469 ,  H01L29/51

    CPC分类号： H01L21/28185 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28238 ,  H01L21/31662 ,  H01L29/513 ,  H01L29/518 ,  H01L21/28194 ,  Y10S148/118

    摘要： A novel process for forming a robust, sub-100 .ANG. oxide is disclosed. Native oxide growth is tightly controlled by flowing pure nitrogen during wafer push and nitrogen with a small amount of oxygen during temperature ramp and stabilization. First, a dry oxidation is performed in oxygen and 13% trichloroethane. Next, a wet oxidation in pyrogenic steam is performed to produce a total oxide thickness of approximately 80 .ANG.. The oxide layer formed is ideally suited for use as a high integrity gate oxide below 100 .ANG.. The invention is particularly useful in devices with advanced, recessed field isolation where sharp silicon edges are difficult to oxidize. For an oxide layer of more than 100 .ANG., a composite oxide stack is used which comprises 40-90 .ANG. of pad oxide formed using the above novel process, and 60-200 .ANG. of deposited oxide.

    摘要翻译： 公开了一种用于形成稳健的，低于100的ANGSTROM氧化物的新方法。 天然氧化物生长通过在晶片推动期间流动纯氮并在温度升高和稳定期间用少量氧气氮气来严格控制。 首先，在氧气和13％三氯乙烷中进行干燥氧化。 接下来，进行热原蒸汽中的湿氧化，以产生约80安培的总氧化物厚度。 形成的氧化物层理想地适合用作低于100安培的高完整性栅极氧化物。 本发明在具有尖锐的硅边缘难以氧化的先进的凹陷磁场隔离的装置中特别有用。 对于超过100个ANGSTROM的氧化物层，使用复合氧化物堆叠，其包括使用上述新方法形成的衬垫氧化物的40-90，以及沉积氧化物的60-200。

    Fabrication of small contact openings in large-scale-integrated devices
    7.
    发明授权
    Fabrication of small contact openings in large-scale-integrated devices 失效
    在大型集成设备中制造小型接触开口

    公开(公告)号：US4136434A

    公开(公告)日：1979-01-30

    申请号：US805408

    申请日：1977-06-10

    申请人： Louis R. Thibault ,  Leopoldo D. Yau

    发明人： Louis R. Thibault ,  Leopoldo D. Yau

    IPC分类号： H01L21/321 ,  H01L21/768 ,  B01J17/00

    CPC分类号： H01L21/32105 ,  H01L21/76888 ,  Y10S148/02 ,  Y10S148/117 ,  Y10S438/949

    摘要： In one embodiment, a relatively thin layer of polysilicon is deposited on an underlying region to which spaced-apart electrical contacts are to be made through a subsequently formed relatively thick insulating layer. The polysilicon is selectively masked by a patterned silicon nitride layer in the regions where contact windows are to be formed. The unmasked polysilicon is then converted to a relatively thick insulating layer in an oxidizing step. Thereafter the silicon nitride portions are removed and the remaining polysilicon is utilized to provide conductive regions in the defined windows. In another embodiment, a relatively thick layer of polysilicon is selectively masked and partially converted to silicon dioxide to define both the insulating layer and the conductive regions. In still another embodiment, a relatively thin layer of polysilicon is patterned and then entirely converted to silicon dioxide to form an insulating layer having windows defined therein.

    摘要翻译： 在一个实施例中，相对薄的多晶硅层沉积在下一个区域上，通过随后形成的相对较厚的绝缘层将间隔开的电触点制成。 在要形成接触窗口的区域中，多晶硅被图案化的氮化硅层选择性地掩蔽。 然后在氧化步骤中将未掩模的多晶硅转变成相对较厚的绝缘层。 此后，去除氮化硅部分，并且使用剩余的多晶硅来在限定的窗口中提供导电区域。 在另一个实施例中，相对厚的多晶硅层被选择性地掩蔽并部分地转换成二氧化硅以限定绝缘层和导电区域。 在另一个实施例中，将相对较薄的多晶硅层图案化，然后完全转化为二氧化硅，以形成其中限定有窗口的绝缘层。

    Integrated dual layer emitter mask and emitter trench for BiCMOS processes
    9.
    发明授权
    Integrated dual layer emitter mask and emitter trench for BiCMOS processes 失效
    用于BiCMOS工艺的集成双层发射极掩模和发射极沟槽

    公开(公告)号：US5856697A

    公开(公告)日：1999-01-05

    申请号：US895270

    申请日：1997-07-14

    申请人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    发明人： Stephen Chambers ,  Brian J. Brown ,  Chan-Hong Chern ,  Robert Chau ,  Leopoldo D. Yau

    IPC分类号： H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L29/66272 ,  H01L21/8249 ,  H01L29/0804 ,  Y10S148/01 ,  Y10S148/011

    摘要： A new method of isolating a polysilicon emitter from the base region of a bipolar transistor, trenching the polysilicon emitter into the semiconductor substrate, and maintaining a consistent base width of a bipolar transistor independent of variations in emitter mask thicknesses is disclosed. The polysilicon emitter isolation provides for better electrical breakdown characteristics between the emitter and the base by protecting the dielectric layer between the polysilicon emitter and base regions from defects and contamination associated with the BiCMOS manufacturing environment. The polysilicon emitter is trenched into the semiconductor substrate in order to reduce transistor operation problems associated with hot electron injection. Consistent base widths improve transistor performance uniformity thereby improving manufacturability and reliability.

    摘要翻译： 公开了一种从双极晶体管的基极区域隔离多晶硅发射极的新方法，将多晶硅发射极沟槽到半导体衬底中，并保持独立于发射极掩模厚度变化的双极晶体管的一致的基底宽度。 多晶硅发射极隔离通过保护多晶硅发射极和基极区域之间的电介质层与BiCMOS制造环境相关的缺陷和污染来提供发射极和基极之间的更好的电击穿特性。 为了减少与热电子注入相关的晶体管操作问题，多晶硅发射极被沟入半导体衬底。 一致的基极宽度提高了晶体管的性能均匀性，从而提高了可制造性和可靠性。