发明授权
- 专利标题： Semiconductor integrated circuit arrangement fabrication method
- 专利标题（中）： 半导体集成电路布置制造方法
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申请号： US857167申请日： 1997-05-15
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公开(公告)号： US5874013A公开(公告)日： 1999-02-23
- 发明人: Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
- 申请人： Takafumi Tokunaga , Sadayuki Okudaira , Tatsumi Mizutani , Kazutami Tago , Hideyuki Kazumi , Ken Yoshioka
- 申请人地址： JPX Tokyo
- 专利权人： Hitachi, Ltd.
- 当前专利权人： Hitachi, Ltd.
- 当前专利权人地址： JPX Tokyo
- 优先权： JPX6-130232 19940613
- 主分类号： H01L21/302
- IPC分类号： H01L21/302 ; H01L21/3065 ; H01L21/311 ; H01L21/70 ; H01L21/768 ; H01L21/77 ; B44C1/22 ; C03C15/00 ; C23F1/00
摘要：
To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other, and selectively obtaining desired dissociated species.
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