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US5969552A Dual loop delay-locked loop 失效
双回路延迟锁定环路

Dual loop delay-locked loop
摘要:
A device and method for synchronizing a local clock to a reference clock. The device uses a frequency acquisition loop and a phase acquisition loop. The frequency acquisition loop delays the reference clock to produce an intermediate clock which falls within the operating range of the phase acquisition loop. The phase acquisition loop then delays the intermediate clock to produce a local clock synchronized to the reference clock.
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