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81 条记录 (耗时 0.019 秒)

    Tracked 3X oversampling receiver
    2.
    发明授权
    Tracked 3X oversampling receiver 有权
    追踪3X过采样接收器

    公开(公告)号：US07203260B2

    公开(公告)日：2007-04-10

    申请号：US10612840

    申请日：2003-07-03

    申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    IPC分类号： H04L7/00 ,  H03L7/095 ,  H03D3/24

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

    摘要： A method of receiving data, in accordance with an embodiment of the present invention, includes the acts of generating a data sampling clock signal and comparing a received clock signal to the data sampling clock signal. The data sampling clock signal is used to sample a data signal into sampled data representing a first zone, a second zone, and a third zone of the data signal. It is then determined which zone of the sampled data has a transition of the data signal and indicating a direction of change for the data sampling clock signal if the first zone or the third zone has the transition.

    摘要翻译： 根据本发明实施例的接收数据的方法包括产生数据采样时钟信号并将接收的时钟信号与数据采样时钟信号进行比较的动作。 数据采样时钟信号用于将数据信号采样成表示数据信号的第一区，第二区和第三区的采样数据。 如果第一区域或第三区域具有转变，则确定采样数据的哪个区域具有数据信号的转变并且指示数据采样时钟信号的改变方向。

    Wide range multi-phase delay-locked loop
    3.
    发明授权
    Wide range multi-phase delay-locked loop 有权
    宽范围多相延时锁定环路

    公开(公告)号：US06876240B2

    公开(公告)日：2005-04-05

    申请号：US10722842

    申请日：2003-11-25

    申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033 ,  H04L7/04 ,  H03L7/06

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

    摘要： A delay locked loop apparatus includes a first delay element to receive a reference signal, to delay the reference signal by a delay time, and to output a first delayed signal. A second delay element is used to receive the first delayed signal, to delay the first signal delayed signal by the delay time, and to output a second delayed signal. Also included is a harmonic lock prevention circuit to receive the reference signal, the first delayed signal, and the second delayed signal, and to adjust the delay time so that a period of each delayed signal is within a predetermined range.

    摘要翻译： 延迟锁定环路装置包括：第一延迟元件，用于接收参考信号，延迟参考信号延迟时间，并输出第一延迟信号。 第二延迟元件用于接收第一延迟信号，以将第一信号延迟信号延迟延迟时间，并输出第二延迟信号。 还包括接收参考信号，第一延迟信号和第二延迟信号的谐波锁定防止电路，并且调整延迟时间，使得每个延迟信号的周期在预定范围内。

    CMOS transceiver with dual current path VCO
    4.
    发明授权
    CMOS transceiver with dual current path VCO 有权
    具有双电流通道VCO的CMOS收发器

    公开(公告)号：US07551909B1

    公开(公告)日：2009-06-23

    申请号：US10651500

    申请日：2003-08-29

    申请人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Young Soo Park ,  Deog-Kyoon Jeong

    IPC分类号： H04B1/06

    CPC分类号： H03L7/107 ,  H03L7/0812 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0995

    摘要： A dual current path voltage controlled oscillator exhibits both the seamless frequency acquisition and uniform VCO gain reduction while preserving an original operating range and phase locked loop characteristics. The present invention provides a quad-channel transceiver comprising a phase locked loop circuit including a voltage controlled oscillator used to generate a clock signal, a FIFO buffer used to store data to be transmitted, a frequency comparator for comparing a reference clock to the generated clock signal from the phase locked loop circuit; and a folded starved inverter circuit contained within the voltage controlled oscillator wherein the folded starved inverter provides two current paths. The dual current paths allow for simultaneous coarse and fine phase tracking. With this low jitter performance and wide operating range, the quad transceiver may be implemented in 0.18-μm CMOS technology, and shows 10−12 bit error rate up to speeds of 3 Gbps.

    摘要翻译： 双电流通道压控振荡器既保留了无缝频率采集和均匀的VCO增益降低，​​又保留了原始工作范围和锁相环特性。 本发明提供了一种四通道收发器，包括一个锁相环电路，该锁相环电路包括用于产生时钟信号的压控振荡器，用于存储要发送的数据的FIFO缓冲器，用于将参考时钟与所产生的时钟进行比较的频率比较器 来自锁相环电路的信号; 以及包含在压控振荡器内的折叠饥饿逆变器电路，其中折叠的饥饿逆变器提供两个电流路径。 双电流路径允许同步粗略和精细的相位跟踪。 凭借这种低抖动性能和广泛的工作范围，四通道收发器可以以0.18微米CMOS技术实现，并显示出10到12位的误码率，达到3 Gbps的速度。

    Frequency comparator with hysteresis between locked and unlocked conditions
    6.
    发明授权
    Frequency comparator with hysteresis between locked and unlocked conditions 有权
    频率比较器在锁定和解锁条件之间具有滞后

    公开(公告)号：US06859107B1

    公开(公告)日：2005-02-22

    申请号：US10356695

    申请日：2003-01-30

    申请人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Gijung Ahn ,  Deog-Kyoon Jeong

    IPC分类号： H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/033 ,  H04L7/04 ,  H03L7/095

    CPC分类号： H04L7/033 ,  H03L7/091 ,  H03L7/113 ,  H03L7/14 ,  H04L7/04 ,  Y10S331/02

    摘要： A frequency comparator apparatus used with a reference clock, a voltage controlled oscillator circuit and a phase locked loop circuit includes a reference loop circuit wherein the reference loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is greater than about a first threshold. Also included is a data loop circuit wherein the data loop circuit is activated when the frequency difference between the reference clock and the voltage controlled oscillator circuit is less than about a second threshold.

    摘要翻译： 与参考时钟，压控振荡器电路和锁相环电路一起使用的频率比较器装置包括参考环路电路，其中当参考时钟和压控振荡器电路之间的频率差大于 约第一个门槛。 还包括数据环路电路，其中当参考时钟和压控振荡器电路之间的频率差小于约第二阈值时，数据环路电路被激活。

    Voltage-controlled oscillator resistant to supply voltage noise
    8.
    发明授权
    Voltage-controlled oscillator resistant to supply voltage noise 失效
    电压控制振荡器可抵抗电源电压噪声

    公开(公告)号：US5955929A

    公开(公告)日：1999-09-21

    申请号：US920336

    申请日：1997-08-27

    申请人： Yongsam Moon ,  Deog-Kyoon Jeong

    发明人： Yongsam Moon ,  Deog-Kyoon Jeong

    IPC分类号： H03K3/013 ,  H03K3/0231 ,  H03K3/03 ,  H03B5/04 ,  H03B5/24

    CPC分类号： H03K3/0322 ,  H03K3/013 ,  H03K3/0231 ,  H03K3/03

    摘要： A voltage-controlled oscillator (VCO) generates an oscillating signal that is substantially resistant to noise fluctuations in the supply voltage. The VCO is a delay-based VCO which preferably includes a compensation circuit for each delay cell and a noise-immune reference current generator for providing a noise-immune bias current to the conditioning circuit of the VCO. The compensation circuit preferably adjusts the capacitance of the delay cell to compensate for the variations in current caused by the supply noise. The noise-immune reference current generator preferably utilizes a configuration of transistors which maintains through at least one transistor a substantially constant current which is used to bias the conditioning circuit.

    摘要翻译： 压控振荡器（VCO）产生基本上抵抗电源电压中的噪声波动的振荡信号。 VCO是基于延迟的VCO，其优选地包括用于每个延迟单元的补偿电路和用于向VCO的调理电路提供无噪声免疫偏置电流的无噪声免疫参考电流发生器。 补偿电路优选地调整延迟单元的电容以补偿由电源噪声引起的电流变化。 噪声免疫参考电流发生器优选地利用晶体管的配置，晶体管通过至少一个晶体管保持用于偏置调理电路的基本上恒定的电流。

    Mixer structure and method of using same
    9.
    发明授权
    Mixer structure and method of using same 失效
    搅拌机结构及其使用方法

    公开(公告)号：US06313688B1

    公开(公告)日：2001-11-06

    申请号：US09709315

    申请日：2000-11-13

    申请人： Kyeongho Lee ,  Deog-Kyoon Jeong

    发明人： Kyeongho Lee ,  Deog-Kyoon Jeong

    IPC分类号： G06F744

    CPC分类号： H04B1/40 ,  H03D7/1441 ,  H03F2200/372 ,  H03H11/22 ,  H03H2011/0494 ,  H03K9/00 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/1974 ,  H04B1/28 ,  H04B1/403

    摘要： A mixer structure and method for using same in accordance with the present invention includes a multi-phase mixer. A VCO includes a plurality of differential delay cells to output a plurality of multi-phase clock signals. The multi-phase mixer can include a load circuit, switch circuit, noise reduction circuit and an input circuit. The switch circuit is coupled to receive the plurality of multi-phase clock signals and includes a first switch array and a second switch array coupled to the load circuit, respectively. The noise reduction circuit coupled to the switch circuit can include a transistor responsive to a bias voltage. The input circuit includes a transistor receiving the input signal. The first switch array includes a first plurality of switches coupled between a first output terminal and a second node, and the second switch array includes a second plurality of switches coupled between a second output terminal and the second node. Preferably, each of the plurality of switches includes two pairs of serially connected transistors, wherein the serially connected transistors are coupled in parallel to provide a symmetric electrical connection for each of two input ports. The mixer and method for using same can be single or double-balanced mixers receiving an RF input signal.

    摘要翻译： 根据本发明的混合器结构及其使用方法包括多相混合器。 VCO包括多个差分延迟单元，以输出多个多相时钟信号。 多相混频器可以包括负载电路，开关电路，降噪电路和输入电路。 开关电路被耦合以接收多个多相时钟信号，并且包括分别耦合到负载电路的第一开关阵列和第二开关阵列。 耦合到开关电路的降噪电路可以包括响应偏置电压的晶体管。 输入电路包括接收输入信号的晶体管。 第一开关阵列包括耦合在第一输出端子和第二节点之间的第一多个开关，并且第二开关阵列包括耦合在第二输出端子和第二节点之间的第二多个开关。 优选地，多个开关中的每一个包括两对串联连接的晶体管，其中串联连接的晶体管并联耦合以为两个输入端口中的每一个提供对称电连接。 混频器和使用它的方法可以是接收RF输入信号的单或双平衡混频器。

    Automatic gain control loop apparatus
    10.
    发明授权
    Automatic gain control loop apparatus 有权
    自动增益控制回路装置

    公开(公告)号：US07035351B1

    公开(公告)日：2006-04-25

    申请号：US09705696

    申请日：2000-11-06

    申请人： Joonbae Park ,  Wonchan Kim ,  Kyeongho Lee ,  Deog-Kyoon Jeong

    发明人： Joonbae Park ,  Wonchan Kim ,  Kyeongho Lee ,  Deog-Kyoon Jeong

    IPC分类号： H03D3/18

    CPC分类号： H04B1/30 ,  H03F3/211 ,  H03F2200/294 ,  H03F2200/372

    摘要： A DC offset cancelling circuit with multiple feedback loops suppresses DC offset voltages within an automatic gain control loop apparatus. The apparatus includes a plurality of gain stages connected in series that receive and amplify an input RF signal. Each gain stage includes a corresponding feedback loop to filter the DC offset voltage accumulated in the respective gain stage.

    摘要翻译： 具有多个反馈环路的DC偏移消除电路抑制自动增益控制环路装置内的DC偏移电压。 该装置包括串联连接的多个增益级，其接收和放大输入RF信号。 每个增益级包括相应的反馈回路以对累积在相应增益级中的DC偏移电压进行滤波。