发明授权
US06845477B2 Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method
失效
用于在晶片测试和半导体测试方法中在许多芯片上并行进行操作测试的半导体测试装置
- 专利标题： Semiconductor test device for conducting an operation test in parallel on many chips in a wafer test and semiconductor test method
- 专利标题（中）： 用于在晶片测试和半导体测试方法中在许多芯片上并行进行操作测试的半导体测试装置
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申请号： US09799581申请日： 2001-03-07
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公开(公告)号： US06845477B2公开(公告)日： 2005-01-18
- 发明人: Hideto Hidaka , Tsukasa Ooishi
- 申请人： Hideto Hidaka , Tsukasa Ooishi
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： McDermott Will & Emery LLP
- 优先权： JP2000-158019 20000529
- 主分类号： G01R1/073
- IPC分类号： G01R1/073 ; G11C29/48 ; H01L21/66 ; G01R31/28 ; G01R31/26
摘要：
A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a test circuit for conducting an operation test on each chip on the test target wafer. Since the test circuit is in a one-to-one relationship with respect to the test target chip, and is arranged on the test wafer other than the test target wafer, the many chips can be simultaneously tested in parallel during the wafer test without increasing an area of the test target chips.
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