公开(公告)号：US07394685B2

公开(公告)日：2008-07-01

申请号：US11582983

申请日：2006-10-19

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G11C11/14

CPC分类号： G11C11/16

摘要： A data write current from a pinned layer to a free layer is larger than a data write current from the free layer to the pinned layer. A data read current is smaller in value than the data write current. In the case where a difference in data read current between a high-resistance state and a low-resistance state is relatively small, a sense amplifier is connected so that the data read current flows from the pinned layer to the free layer, namely from a source line to a bit line.

摘要翻译： 从固定层到自由层的数据写入电流大于从自由层到被钉扎层的数据写入电流。 数据读取电流的值比数据写入电流小。 在高电阻状态和低电阻状态之间的数据读取电流的差异相对较小的情况下，连接读出放大器，使得数据读取电流从固定层流向自由层，即从 源线到位线。

公开(公告)号：US07256644B2

公开(公告)日：2007-08-14

申请号：US10628384

申请日：2003-07-29

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： G05F1/10

CPC分类号： G11C5/063 ,  G11C5/14 ,  G11C5/144 ,  G11C5/147 ,  G11C2207/2227 ,  Y10T307/391 ,  Y10T307/461 ,  Y10T307/696 ,  Y10T307/724 ,  Y10T307/747

摘要： Resistance elements are inserted into a main power supply line and a main ground line so that offset differential amplifiers receive voltages developed across the same. The differential amplifiers control transistors connected to a sub power supply line and a sub ground line. Thus, a leakage current flowing from the sub power supply line to the main ground line and that flowing from the main power supply line to the sub ground line are regularly kept constant. Consequently, it is possible to prevent an operation delay in an initial stage of a standby state while keeping an effect of reducing a subthreshold leakage current in a semiconductor circuit device having a hierarchical power supply structure.

摘要翻译： 电阻元件插入主电源线和主接地线，使得偏移差分放大器接收在其上产生的电压。 差分放大器控制连接到副电源线和次接地线的晶体管。 因此，从副电源线流向主接地线并从主电源线流向副接地线的漏电流规则地保持恒定。 因此，可以在保持具有分级供电结构的半导体电路装置中降低亚阈值泄漏电流的效果的同时防止在待机状态的初始阶段的操作延迟。

公开(公告)号：US20060152971A1

公开(公告)日：2006-07-13

申请号：US11374062

申请日：2006-03-14

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C11/14

CPC分类号： G11C11/15 ,  G11C11/16

摘要： During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

公开(公告)号：US06862209B2

公开(公告)日：2005-03-01

申请号：US10361770

申请日：2003-02-11

申请人： Hideto Hidaka ,  Masatoshi Ishikawa ,  Tsukasa Ooishi

发明人： Hideto Hidaka ,  Masatoshi Ishikawa ,  Tsukasa Ooishi

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11C11/00 ,  G11C11/14

CPC分类号： G11C11/16

摘要： An access transistor in an MTJ memory cell, which is one of transistors connected to a read current path, is fabricated with a semiconductor layer formed on an insulating film on a semiconductor substrate SUB, and includes impurity regions, a gate region and a body region. That is, the access transistor is fabricated with an SOI (Silicon On Insulator) structure in order to reduce an off-leak current.

摘要翻译： 在连接到读取电流路径的晶体管之一的MTJ存储单元中的存取晶体管由在半导体衬底SUB上的绝缘膜上形成的半导体层制成，并且包括杂质区域，栅极区域和体区域 。 也就是说，存取晶体管是用SOI（绝缘体上硅）结构制造的，以便减少漏电流。

公开(公告)号：US06845477B2

公开(公告)日：2005-01-18

申请号：US09799581

申请日：2001-03-07

申请人： Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G01R1/073 ,  G11C29/48 ,  H01L21/66 ,  G01R31/28 ,  G01R31/26

CPC分类号： G11C29/48

摘要： A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a test circuit for conducting an operation test on each chip on the test target wafer. Since the test circuit is in a one-to-one relationship with respect to the test target chip, and is arranged on the test wafer other than the test target wafer, the many chips can be simultaneously tested in parallel during the wafer test without increasing an area of the test target chips.

摘要翻译： 测试目标晶片上的多个测试目标芯片通过晶片接触器同时并电耦合到测试晶片上的多个芯片。 测试晶片上的每个芯片具有用于对测试目标晶片上的每个芯片进行操作测试的测试电路。 由于测试电路相对于测试目标芯片是一对一的关系，并且被布置在除了测试目标晶片之外的测试晶片上，所以许多芯片可以在晶片测试期间并行同时测试而不增加 测试目标芯片的一个区域。

公开(公告)号：US06757191B2

公开(公告)日：2004-06-29

申请号：US10222793

申请日：2002-08-19

申请人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

发明人： Tsukasa Ooishi ,  Hideto Hidaka ,  Masatoshi Ishikawa

IPC分类号： G11C1114

CPC分类号： G11C11/16

摘要： A tunneling magneto-resistance element of each MTJ (magnetic tunnel junction) memory cell is connected between a bit line and a strap. Each strap is shared by a plurality of tunneling magneto-resistance elements that are located adjacent to each other in the row direction in the same sub array. Each access transistor is connected between a corresponding strap and a ground voltage, and turned ON/OFF in response to a corresponding word line. Since data read operation can be conducted with the structure that does not have an access transistor for every tunneling magneto-resistance element, the array area can be reduced.

摘要翻译： 每个MTJ（磁性隧道结）存储单元的隧道磁阻元件连接在位线和带之间。 每个带由多个相同子阵列中的行方向上彼此相邻的隧道磁阻元件共享。 每个存取晶体管连接在对应的带和接地电压之间，并响应于相应的字线而导通/截止。 由于可以对每个隧道磁阻元件不具有存取晶体管的结构进行数据读取操作，因此可以减小阵列面积。

公开(公告)号：US06621306B2

公开(公告)日：2003-09-16

申请号：US10036406

申请日：2002-01-07

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： H03K19094

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356121

摘要： A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.

公开(公告)号：US06469327B1

公开(公告)日：2002-10-22

申请号：US08900515

申请日：1997-07-25

申请人： Kenichi Yasuda ,  Hideto Hidaka ,  Mikio Asakura ,  Tsukasa Ooishi ,  Kei Hamade

发明人： Kenichi Yasuda ,  Hideto Hidaka ,  Mikio Asakura ,  Tsukasa Ooishi ,  Kei Hamade

IPC分类号： H01L2710

CPC分类号： H01L23/50 ,  H01L24/06 ,  H01L24/48 ,  H01L27/0207 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4826 ,  H01L2224/73215 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01024 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

摘要： Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.

摘要翻译： 垫片排列在半导体芯片的中心区域中，并且还布置在芯片的中心部分的外周部分。 外周部分的焊盘与安装芯片的芯片焊盘电连接，绝缘材料插入其间。 通过芯片焊盘的寄生电容可以使供给位于外周部的焊盘的电位稳定，并且能够通过在树脂密封后除去一部分模制树脂来容易地外部监视焊盘的电位。 此外，由于焊盘的水平排列，可以将电压降压转换器布置成与焊盘和芯片的外周边一致，而不会造成区域损失。 在测试操作中，切换电路将焊盘的功能切换到另一焊盘，使得十字形布置的焊盘等价地布置成一行。

公开(公告)号：US06337583B1

公开(公告)日：2002-01-08

申请号：US09571270

申请日：2000-05-15

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： H03K19094

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356121

摘要： A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.

公开(公告)号：US6055206A

公开(公告)日：2000-04-25

申请号：US274623

申请日：1999-03-23

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/08 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1072

摘要： In a synchronous semiconductor memory device of the present invention, a main word driver and a sub decode driver have a function to take in a row decode signal in response to activation of a bank and to maintain the state of the row decode signal. Accordingly, of the circuits associated with row selection, a row pre-decoder, a row decoder and a row system control circuit can operate under a hierarchical power supply structure.

摘要翻译： 在本发明的同步半导体存储器件中，主字驱动器和子解码驱动器具有响应于存储体的激活而获取行解码信号并保持行解码信号的状态的功能。 因此，与行选择相关联的电路中，行预解码器，行解码器和行系统控制电路可以在分层电源结构下操作。