发明授权
US06889313B1 Selection of decoder output from two different length instruction decoders 有权
从两个不同长度的指令解码器中选择解码器输出

Selection of decoder output from two different length instruction decoders
摘要:
A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.
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