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1.发明授权Decoding next instruction of different length without length mode indicator change upon length change instruction detection 有权解码不同长度的下一条指令，长度模式指示符在长度变化指令检测时发生变化公开(公告)号：US06678818B1
公开(公告)日：2004-01-13
申请号：US09562715
申请日：2000-05-02
IPC分类号： G06F930
CPC分类号： G06F9/3822 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3814 , G06F9/3885
摘要： A decode unit (20) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry (50-60) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX6,MUX7) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector (70) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.
摘要翻译： 解码单元（20）解码处理器中的指令。 这些指令包括在第一指令模式下具有第一长度的指令和在第二指令模式中的第二较短长度的指令。 解码单元具有对指令进行解码的解码电路（50-60）。 寄存器保持指令模式并产生指令模式信号。 开关电路（MUX6，MUX7）响应于指令模式信号，以根据指令模式从解码单元输出解码指令。 提供检测器（70），用于在第二指令模式中检测第二较短长度的长度变化指令，其指示后续指令是第一长度。 检测器还临时改变指令模式信号的状态，以允许第一长度指令被解码而不改变保持在寄存器中的指令模式。
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2.发明授权公开(公告)号：US06889313B1
公开(公告)日：2005-05-03
申请号：US09563634
申请日：2000-05-02
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/3822 , G06F9/3836 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.
摘要翻译： 解码单元包括分别连接以接收第一和第二预定长度的比特序列的第一和第二解码器。 第一和第二解码器并行操作以产生相应的输出。 开关根据控制实际需要解码的位序列的长度的处理器的指令模式来选择输出之一。
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3.发明授权Multiple execution of instruction loops within a processor without accessing program memory 有权多处理处理器内的指令循环，无需访问程序存储器公开(公告)号：US06959379B1
公开(公告)日：2005-10-25
申请号：US09562542
申请日：2000-05-02
申请人： Laurent Wojcieszak , Andrew Cofler
发明人： Laurent Wojcieszak , Andrew Cofler
CPC分类号： G06F9/381 , G06F9/30149 , G06F9/325
摘要： A method of executing loops in a computer system is described. The computer system has a sequence of instructions held in program memory and a prefetch buffer which holds instructions fetched from the memory ready for supply to a decoder of the computer system. If the size of the loop to be executed is such that it can by holly contained within the prefetch buffer, this is detected and a lock is put on the prefetch buffer to retain the loop within it while the loop is executed a requisite number of times. This thus allows power to be saved and reduces the overhead on the memory access buffers. According to another aspect, loops can be “skipped” by holding a value of zero in the loop counter register.
摘要翻译： 描述了在计算机系统中执行循环的方法。 计算机系统具有保存在程序存储器中的指令序列和保存从存储器取出的指令的预取缓冲器，准备供给计算机系统的解码器。 要执行的循环的大小使得它可以通过冬青包含在预取缓冲器中，这被检测到，并且锁定放在预取缓冲器上以将循环保持在其中，同时循环被执行必要的次数 。 这因此允许保存电力并减少存储器访问缓冲器的开销。 根据另一方面，可以通过在循环计数器寄存器中保持零值来“跳过”循环。
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公开(公告)号：US07013256B2
公开(公告)日：2006-03-14
申请号：US10021269
申请日：2001-12-12
CPC分类号： G06F11/3632 , G06F9/30072 , G06F11/3648
摘要： A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.
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5.发明申请Computer system with debug facility for debugging a processor capable of predicated execution 有权具有调试功能的计算机系统，用于调试能够进行预定执行的处理器公开(公告)号：US20060184775A1
公开(公告)日：2006-08-17
申请号：US11384024
申请日：2006-03-17
IPC分类号： G06F9/44
CPC分类号： G06F11/3656 , G06F9/3842
摘要： A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.
摘要翻译： 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。
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公开(公告)号：US06711668B1
公开(公告)日：2004-03-23
申请号：US09562718
申请日：2000-05-02
申请人： Laurent Wojcieszak , Andrew Cofler
发明人： Laurent Wojcieszak , Andrew Cofler
IPC分类号： G06F938
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3853
摘要： A prefetch buffer is described which supports a computer system having a plurality of different instruction modes. The number of storage locations which are read out of the prefetch buffer during each machine cycle is controlled in dependence on the instruction mode. Thus the prefetch buffer allows a number of different instruction modes to be support and hides memory access latency.
摘要翻译： 描述了一种预取缓冲器，其支持具有多个不同指令模式的计算机系统。 根据指令模式控制在每个机器周期期间从预取缓冲器中读出的存储位置的数量。 因此，预取缓冲器允许支持多种不同的指令模式并隐藏存储器访问等待时间。
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7.发明授权Computer system with a debug facility for a pipelined processor using predicated execution 有权具有使用预定执行的流水线处理器调试功能的计算机系统公开(公告)号：US07441109B2
公开(公告)日：2008-10-21
申请号：US11384024
申请日：2006-03-17
IPC分类号： G06F7/38
CPC分类号： G06F11/3656 , G06F9/3842
摘要： A computer system with enhanced integrated debug facilities is described. According to one aspect, step-by-step execution of an instruction sequence is implemented where each instruction is guarded. If, after guard resolution, the instruction is committed, a divert routine is executed. If the instruction is not committed, the next instruction in the sequence is executed. According to another aspect, a stall state can be set at the decode unit either by reading stall attributes associated with debug instructions, or responsive to a stall command from an on-chip emulation unit.
摘要翻译： 描述了一种具有增强型集成调试功能的计算机系统。 根据一个方面，执行指令序列的逐步执行，其中每个指令被保护。 如果在保护解决之后，执行指令，则执行转移程序。 如果指令未提交，则执行该顺序中的下一条指令。 根据另一方面，可以通过读取与调试指令相关联的失速属性，或响应来自片上仿真单元的失速命令，在解码单元处设置失速状态。
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8.发明授权Computer system with two debug watch modes for controlling execution of guarded instructions upon breakpoint detection 有权具有两个调试监视模式的计算机系统，用于在断点检测时控制执行保护指令公开(公告)号：US07240185B2
公开(公告)日：2007-07-03
申请号：US09748785
申请日：2000-12-22
IPC分类号： G06F11/36
CPC分类号： G06F11/3656
摘要： A computer system is provided with precise and non-precise watch modes. The computer system is a pipelined system in which the fate of an instruction is determined at the decode stage. Once instructions have been decoded, it is not possible for them to be “killed” later in the pipeline. According to the precise watch mode, instructions are held at the decode stage until the guard value has been resolved to determine whether or not that instruction is committed. Actions of the decode unit are determined in dependence on whether or not the instruction is committed when the guard has been resolved. According to a non-precise watch mode, instructions continue to be decoded and executed normally until a breakpoint instruction has had its guard resolved. At that point, an on-chip emulator can take over operations of the processor in a divert mode. The computer system can take into account different intrusion levels while implementing the watch modes.
摘要翻译： 计算机系统提供精确和非精确的手表模式。 计算机系统是在解码阶段确定指令的命运的流水线系统。 一旦指令被解码，它们不可能在后期被“杀死”。 根据精确的观察模式，在解码阶段保持指令，直到保护值被解析以确定该指令是否被提交。 解码单元的动作取决于当防护件已被解决时是否提交指令。 根据不精确的观察模式，指令继续被解码并正常执行，直到断点指令得到保护解决为止。 在这一点上，片上仿真器可以在转接模式下接管处理器的操作。 计算机系统可以在实现手表模式时考虑到不同的入侵级别。
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公开(公告)号：US06742131B1
公开(公告)日：2004-05-25
申请号：US09562717
申请日：2000-05-02
申请人： Laurent Wojcieszak , Andrew Cofler
发明人： Laurent Wojcieszak , Andrew Cofler
IPC分类号： G06F132
CPC分类号： G06F9/30145 , G06F9/30156 , G06F9/30181 , G06F9/30189 , G06F9/30196 , G06F9/3802 , G06F9/3814 , G06F9/3822
摘要： An instruction prefetch buffer is described which has a powersave mechanism. A set of output devices of an instruction supply mechanism each have a stop switch which either pass on a changed bit sequence or the previously supplied bit sequence. If the previously supplied bit sequence is supplied, no power is utilized in that machine cycle.
摘要翻译： 描述了具有电源保护机制的指令预取缓冲器。 指令供给机构的一组输出装置各自具有停止开关，该停止开关通过改变的位序列或先前提供的位序列。 如果提供先前提供的位序列，则在该机器周期中不使用电源。
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公开(公告)号：US06718452B1
公开(公告)日：2004-04-06
申请号：US09563610
申请日：2000-05-02
申请人： Laurent Wojcieszak , Sonia Ferrante
发明人： Laurent Wojcieszak , Sonia Ferrante
IPC分类号： G06F1200
CPC分类号： G06F9/3814 , G06F9/3802 , G11C8/16
摘要： A storage array is described which is specifically adapted to support a specific set of instruction modes of a processor. A first set of storage cells have a write input and a single read output. Second and third sets of storage cells each have a write input and only two read outputs. A fourth set of storage cells each have a write input and only three outputs. All the write inputs are addressable in common by a single write address and the read outputs are individually selectable responsive to a read pointer.
摘要翻译： 描述了一种存储阵列，其特别适用于支持处理器的特定指令模式集合。 第一组存储单元具有写入输入和单个读取输出。 第二组和第三组存储单元都具有写入输入和仅两个读取输出。 第四组存储单元分别具有写入输入和仅三个输出。 所有写入输入通过单个写入地址可寻址，并且读取输出可以响应于读取指针而单独选择。
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