Invention Grant
- Patent Title: Fabrication method of semiconductor integrated circuit device
- Patent Title (中): 半导体集成电路器件的制造方法
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Application No.: US11750371Application Date: 2007-05-18
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Publication No.: US07351597B2Publication Date: 2008-04-01
- Inventor: Yuji Wada , Susumu Kasukabe , Takehiko Hasebe , Yasunori Narizuka , Akira Yabushita , Terutaka Mori , Akio Hasebe , Yasuhiro Motoyama , Teruo Shoji , Masakazu Sueyoshi
- Applicant: Yuji Wada , Susumu Kasukabe , Takehiko Hasebe , Yasunori Narizuka , Akira Yabushita , Terutaka Mori , Akio Hasebe , Yasuhiro Motoyama , Teruo Shoji , Masakazu Sueyoshi
- Applicant Address: JP Tokyo
- Assignee: Renesas Technology Corp.
- Current Assignee: Renesas Technology Corp.
- Current Assignee Address: JP Tokyo
- Agency: Antonelli, Terry, Stout & Kraus, LLP.
- Priority: JP2003-075429 20030319
- Main IPC: H01L21/66
- IPC: H01L21/66

Abstract:
The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.
Public/Granted literature
- US20070218572A1 FABRICATION METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Public/Granted day:2007-09-20
Information query
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