发明授权
- 专利标题: Dynamic control of memory interface timing
- 专利标题(中): 动态控制存储器接口时序
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申请号: US11925717申请日: 2007-10-26
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公开(公告)号: US07589556B1公开(公告)日: 2009-09-15
- 发明人: Johnson Tan , Andrew Bellis , Philip Clarke , Yan Chong , Joseph Huang , Michael H. M. Chu , Chiakang Sung
- 申请人: Johnson Tan , Andrew Bellis , Philip Clarke , Yan Chong , Joseph Huang , Michael H. M. Chu , Chiakang Sung
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Townsend and Townsend and Crew LLP
- 主分类号: G06F7/38
- IPC分类号: G06F7/38
摘要:
Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.
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