Coated article and method for repairing a coated surface

    公开(公告)号:US07093335B2

    公开(公告)日:2006-08-22

    申请号:US10189087

    申请日:2002-07-03

    IPC分类号: B23P6/00

    摘要: A method is provided for repairing a surface portion of an article including a metallic environmental resistant coating on a substrate. The coating includes a coating outer portion bonded with the substrate through a diffusion zone that includes at least one feature, for example Al and/or an intermetallic phase, in an amount detrimental to application of a metallic replacement coating and/or repair of the article. The method comprises removing the coating outer portion to expose a surface of the diffusion zone. The substrate and the diffusion zone are heated at a temperature and for a time sufficient to diffuse and/or dissolve at least a portion of the at least one feature in the exposed surface and in a portion of the diffusion zone beneath the exposed surface to a level below the detrimental amount. This provides a replacement surface portion integral with diffusion zone. Then a metallic replacement coating outer portion is applied to the replacement surface portion. Provided is a coated article comprising a substrate and a metallic environmental resistant coating bonded with the substrate. The coating comprises an inner modified portion of the substrate integral with the substrate, an outer diffusion zone integral with the inner portion, and a metallic environmental resistant coating outer portion integral with the outer diffusion zone. In some forms, the coated article includes a thermal barrier coating over the metallic coating outer portion.

    Coating article and method for repairing a coated surface
    5.
    发明授权
    Coating article and method for repairing a coated surface 有权
    涂层制品和修补涂层表面的方法

    公开(公告)号:US06605364B1

    公开(公告)日:2003-08-12

    申请号:US09618576

    申请日:2000-07-18

    IPC分类号: B32B1504

    摘要: A method is provided for repairing a surface portion of an article including a metallic environmental resistant coating on a substrate. The coating includes a coating outer portion bonded with the substrate through a diffusion zone that includes at least one feature, for example Al and/or an intermetallic phase, in an amount detrimental to application of a metallic replacement coating and/or repair of the article. The method comprises removing the coating outer portion to expose a surface of the diffusion zone. The substrate and the diffusion zone are heated at a temperature and for a time sufficient to diffuse and/or dissolve at least a portion of the at least one feature in the exposed surface and in a portion of the diffusion zone beneath the exposed surface to a level below the detrimental amount. This provides a replacement surface portion integral with diffusion zone. Then a metallic replacement coating outer portion is applied to the replacement surface portion. Provided is a coated article comprising a substrate and a metallic environmental resistant coating bonded with the substrate. The coating comprises an inner modified portion of the substrate integral with the substrate, an outer diffusion zone integral with the inner portion, and a metallic environmental resistant coating outer portion integral with the outer diffusion zone. In some forms, the coated article includes a thermal barrier coating over the metallic coating outer portion.

    摘要翻译: 提供一种用于修复在基材上包含金属耐环境涂层的制品的表面部分的方法。 涂层包括通过扩散区与基底结合的涂层外部部分,该扩散区包括至少一个特征,例如Al和/或金属间相,其量不利于施加金属替代涂层和/或修复物品 。 该方法包括去除涂层外部部分以暴露扩散区域的表面。 衬底和扩散区在足以在暴露表面和暴露表面下方的扩散区的一部分中的至少一部分的至少一部分扩散和/或溶解的温度下加热至 低于有害量。 这提供了与扩散区一体的替换表面部分。 然后将金属替换涂层外部施加到更换表面部分。 本发明提供一种包含基材和与该基材结合的耐金属金属涂层的涂布制品。 所述涂层包括与所述基底一体的所述基底的内部改性部分,与所述内部一体的外部扩散区,以及与所述外部扩散区一体的金属防环境涂层外部。 在一些形式中,涂覆制品在金属涂层外部部分上包括热障涂层。

    Apparatus for memory interface configuration
    7.
    发明授权
    Apparatus for memory interface configuration 有权
    记忆体接口配置装置

    公开(公告)号:US08223584B1

    公开(公告)日:2012-07-17

    申请号:US12431848

    申请日:2009-04-29

    申请人: Philip Clarke

    发明人: Philip Clarke

    IPC分类号: G11C8/00

    摘要: An apparatus includes a memory circuit and an interface circuit. The interface circuit is coupled to the memory circuit. The interface circuit selects a phase value of clock signal adapted to clock the memory circuit.

    摘要翻译: 一种装置包括存储电路和接口电路。 接口电路耦合到存储器电路。 接口电路选择适于对存储器电路进行时钟的时钟信号的相位值。

    DQS re sync calibration
    8.
    发明授权
    DQS re sync calibration 有权
    DQS重新同步校准

    公开(公告)号:US07791375B1

    公开(公告)日:2010-09-07

    申请号:US12501398

    申请日:2009-07-10

    申请人: Philip Clarke

    发明人: Philip Clarke

    IPC分类号: H03K19/00

    摘要: Read interface circuitry is disclosed that facilitates using a source-synchronous clock signal to calibrate the read interface. In one embodiment, configurable read interface circuitry allows a particular read path to be configured for use in calibrating a read interface of the destination device. In particular, a plurality of read paths are provided, each read path having a configurable multiplexor (“mux”) coupled to a capture register of the read path such that the mux can be configured to select either an input coupled to an inverted output of the capture register or an input coupled to a prior register in the read data path. When the inverted output of the capture register is selected, a source-synchronous clock signal (e.g., DQS or delayed DQS signal) provided at the capture register's clock input results in a toggle signal at the capture register's output. In one embodiment, that toggle signal is provided to a re-sync register clocked by a re-sync clock signal. This toggle signal, together with another toggle signal generated at a toggle register coupled to the re-sync clock signal, are compared for various possible phases of the re-sync clock signal to determine a preferred phase of the re-sync clock signal. For other read paths, a mux coupled to a similar capture register is configured to select an input coupled to a prior register in the read path so that the read path can act as a path for incoming data signals (e.g., DQ signals).

    摘要翻译: 公开了读接口电路,便于使用源同步时钟信号来校准读接口。 在一个实施例中,可配置的读接口电路允许将特定读路径配置为用于校准目的地设备的读接口。 特别地,提供多个读取路径,每个读取路径具有耦合到读取路径的捕获​​寄存器的可配置多路复用器(“多路复用器”),使得多路复用器可被配置为选择耦合到反向输出的输入 捕获寄存器或耦合到读取数据路径中的先前寄存器的输入。 当选择捕捉寄存器的反相输出时,在捕捉寄存器的时钟输入端提供的源同步时钟信号(例如DQS或延迟DQS信号)在捕捉寄存器的输出端产生一个触发信号。 在一个实施例中,该触发信号被提供给由再同步时钟信号计时的重新同步寄存器。 对于重新同步时钟信号的各种可能的相位,将该触发信号与在耦合到重新同步时钟信号的触发寄存器处产生的另一个触发信号相比较,以确定重新同步时钟信号的优选相位。 对于其他读取路径,耦合到类似捕获寄存器的复用器被配置为选择耦合到读取路径中的先前寄存器的输入,使得读取路径可以用作输入数据信号(例如,DQ信号)的路径。

    Read-leveling implementations for DDR3 applications on an FPGA
    9.
    发明授权
    Read-leveling implementations for DDR3 applications on an FPGA 有权
    FPGA上DDR3应用程序的读取级别实现

    公开(公告)号:US07593273B2

    公开(公告)日:2009-09-22

    申请号:US11935310

    申请日:2007-11-05

    IPC分类号: G11C7/10

    摘要: Circuits, methods, and apparatus for transferring data from a device's input clock domain to a core clock domain. One example achieves this by using a retiming element between input and core circuits. The retiming element is calibrated by incrementally sweeping a delay and receiving data at each increment. Minimum and maximum delays where data is received without errors are averaged. This average can then be used to adjust the timing of a circuit element inserted in an input path between an input register clocked by an input strobe signal and an output register clocked by a core clock signal. In one example, an input signal may be delayed by an amount corresponding to the delay setting. In other examples, each input signal is registered using an intermediate register between the input register and the output register, where a clock signal is delayed by an amount corresponding to the delay setting.

    摘要翻译: 用于将数据从设备的输入时钟域传送到核心时钟域的电路,方法和装置。 一个例子是通过在输入和电路之间使用重新定时元件实现这一点。 重新定时元素通过逐渐扫描延迟并在每个增量处接收数据进行校准。 平均接收无差错数据的最小和最大延迟。 然后可以使用该平均值来调整插入由输入选通信号计时的输入寄存器和由核心时钟信号计时的输出寄存器之间的输入路径中的电路元件的定时。 在一个示例中,输入信号可以被延迟与延迟设置相对应的量。 在其他示例中,使用输入寄存器和输出寄存器之间的中间寄存器来注册每个输入信号,其中时钟信号被延迟与延迟设置相对应的量。

    Dynamic control of memory interface timing
    10.
    发明授权
    Dynamic control of memory interface timing 有权
    动态控制存储器接口时序

    公开(公告)号:US07589556B1

    公开(公告)日:2009-09-15

    申请号:US11925717

    申请日:2007-10-26

    IPC分类号: G06F7/38

    摘要: Circuits, methods, and apparatus for the dynamic control of calibration data that adjusts the timing of input and output signals on an integrated circuit. This dynamic control allows input and output circuits to self-calibrate by compensating for temperature and voltage changes in an efficient manner, without the need for device reconfiguration. Calibration settings can be maintained while new calibration settings are loaded. Skew between clock and data signals, as well as among multiple data signals, can be reduced. Dynamic control is achieved while consuming only a minimal resources including route paths.

    摘要翻译: 用于动态控制校准数据的电路,方法和装置,用于调整集成电路上的输入和输出信号的时序。 该动态控制允许输入和输出电路通过以有效的方式补偿温度和电压变化而进行自校准,而不需要对器件重新配置。 加载新的校准设置时,可以保持校准设置。 可以减少时钟和数据信号之间以及多个数据信号之间的偏移。 实现动态控制,同时仅消耗包括路由路径在内的最小资源。