发明授权
US07685485B2 Functional failure analysis techniques for programmable integrated circuits
失效
用于可编程集成电路的功能故障分析技术
- 专利标题： Functional failure analysis techniques for programmable integrated circuits
- 专利标题（中）： 用于可编程集成电路的功能故障分析技术
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申请号： US10698739申请日： 2003-10-30
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公开(公告)号： US07685485B2公开(公告)日： 2010-03-23
- 发明人: Binh Vo , Wan-Pin Hung , David Huang , Peter Boyle , Qi Richard Chen , Kaiyu Ren , Adam J. Wright , John DiCosola , Laiq Chughtai , Seng Yew Lim
- 申请人： Binh Vo , Wan-Pin Hung , David Huang , Peter Boyle , Qi Richard Chen , Kaiyu Ren , Adam J. Wright , John DiCosola , Laiq Chughtai , Seng Yew Lim
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 代理机构： Townsend and Townsend and Crew LLP
- 主分类号： G01R31/28
- IPC分类号： G01R31/28
摘要：
Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.
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