公开(公告)号：US08779754B2

公开(公告)日：2014-07-15

申请号：US13019277

申请日：2011-02-01

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： H03K5/14 ,  H03K5/13 ,  H03K5/15

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US07940082B1

公开(公告)日：2011-05-10

申请号：US12053183

申请日：2008-03-21

申请人： Adam J. Wright

发明人： Adam J. Wright

IPC分类号： H03K19/177

CPC分类号： H03K19/1737

摘要： Circuit for selectively using static or dynamic select signals inside an integrated circuit, including a first transistor connecting a static select signal to a dynamic route select output line when a dynamic select CRAM signal is at a first logical level, and a second transistor connecting a dynamic select signal to the dynamic route select output line when the dynamic select CRAM signal is at a second logical level. The circuit further comprises a dynamic select CRAM register that contains a logical value to indicate whether the dynamic select signal bypasses the static select signal. The dynamic select CRAM register is connected to the second transistor gate, and to an inverter whose output is connected to the first transistor gate.

摘要翻译： 用于选择性地使用集成电路内的静态或动态选择信号的电路，包括当动态选择CRAM信号处于第一逻辑电平时将静态选择信号连接到动态路径选择输出线的第一晶体管，以及连接动态 当动态选择CRAM信号处于第二逻辑电平时，选择信号到动态路由选择输出线路。 电路还包括动态选择CRAM寄存器，其包含用于指示动态选择信号是否绕过静态选择信号的逻辑值。 动态选择CRAM寄存器连接到第二晶体管栅极，并连接到其输出连接到第一晶体管栅极的反相器。

公开(公告)号：US07884619B1

公开(公告)日：2011-02-08

申请号：US12566157

申请日：2009-09-24

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： G01R35/00 ,  G01R23/175 ,  G08B23/00 ,  H03L7/00

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US07685485B2

公开(公告)日：2010-03-23

申请号：US10698739

申请日：2003-10-30

申请人： Binh Vo ,  Wan-Pin Hung ,  David Huang ,  Peter Boyle ,  Qi Richard Chen ,  Kaiyu Ren ,  Adam J. Wright ,  John DiCosola ,  Laiq Chughtai ,  Seng Yew Lim

发明人： Binh Vo ,  Wan-Pin Hung ,  David Huang ,  Peter Boyle ,  Qi Richard Chen ,  Kaiyu Ren ,  Adam J. Wright ,  John DiCosola ,  Laiq Chughtai ,  Seng Yew Lim

IPC分类号： G01R31/28

CPC分类号： G01R31/31935 ,  G01R31/31705 ,  G01R31/318516

摘要： Techniques are provided for isolating failed routing resources on a programmable circuit. Failing test patterns and the test logs are fed to a Statistical Failure Isolation (SFI) tool. The SFI tool extracts failing paths from the test patterns. A statistical analysis is performed on interconnect resources related to failing paths. The resources on the paths are then tallied to create a histogram of resources. These resources are then be fed into an Adaptive Failure Isolation (AFI) tool to auto-generate verification patterns. A tester uses the verification patterns to isolate failed interconnect resources.

摘要翻译： 提供了用于隔离可编程电路上的故障路由资源的技术。 失败的测试模式和测试日志被馈送到统计失效隔离（SFI）工具。 SFI工具提取测试模式的失败路径。 对与故障路径相关的互连资源进行统计分析。 然后对路径上的资源进行计算，以创建资源直方图。 然后将这些资源馈送到自适应故障隔离（AFI）工具中，以自动生成验证模式。 测试人员使用验证模式来隔离故障的互连资源。

公开(公告)号：US08786301B1

公开(公告)日：2014-07-22

申请号：US12817174

申请日：2010-06-16

申请人： Adam J. Wright ,  Joseph W. Foerstel ,  Mark Andrew Banke ,  Ken A. Ito

发明人： Adam J. Wright ,  Joseph W. Foerstel ,  Mark Andrew Banke ,  Ken A. Ito

IPC分类号： G01R31/20

CPC分类号： G01R31/2889

摘要： A system for testing a device under test (DUT), in which electrical coupling among a module board, a low profile connector, and, a DIB is established by applying a pressure on the module board toward the DUT, is provided. The system includes a test head bracket secured inside a test head, the test head bracket includes the module board having a first section including a plurality of connectors to couple a test analyzer to the module board, a second section including a plurality of contacts pads to electrically couple the module board to the DUT, and, a flexible board to enable the first section to be placed at an angle with respect to the second section. The test head bracket also includes a module board stiffener mechanically securing the first section and the second section to the test head and the low profile connector electrically couples the module board to the DUT.

摘要翻译： 提供了一种用于测试被测器件（DUT）的系统，其中通过向模块板施加压力来建立模块板，低剖面连接器和DIB之间的电耦合。 该系统包括固定在测试头内的测试头支架，测试头托架包括模块板，模块板具有第一部分，该第一部分包括多个连接器以将测试分析仪耦合到模块板;第二部分，包括多个接触垫 将模块板电耦合到DUT，以及柔性板，以使得第一部分能够相对于第二部分以一定角度放置。 测试头支架还包括将第一部分和第二部分机械地固定到测试头的模块板加强件，并且小型连接器将模块板电耦合到DUT。

公开(公告)号：US07795909B1

公开(公告)日：2010-09-14

申请号：US12103567

申请日：2008-04-15

申请人： Kenneth T. Daxer ,  Adam J. Wright

发明人： Kenneth T. Daxer ,  Adam J. Wright

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17776 ,  H03K19/17764

摘要： A programmable logic device that receives and stores configuration data in configurable random-access-memory has differential signal input buffer circuitry for receiving the configuration data from a configuration device in differential signal form at high speeds. The programmable logic device may have clock and data recovery circuitry that receives a reference clock and that generates a corresponding internal clock that is used for receiving the configuration data. Error detection circuitry may be used to detect errors occurring during data transmission. The configuration device may have a serializer that serializes parallel configuration data received from memory and differential signal output driver circuitry that provides the configuration data in differential signal form to the programmable logic device.

摘要翻译： 在可配置随机存取存储器中接收并存储配置数据的可编程逻辑器件具有用于以高速以差分信号形式从配置器件接收配置数据的差分信号输入缓冲器电路。 可编程逻辑器件可以具有接收参考时钟并且产生用于接收配置数据的相应内部时钟的时钟和数据恢复电路。 错误检测电路可用于检测在数据传输期间发生的错误。 配置装置可以具有串行化串行化从存储器接收的并行配置数据和差分信号输出驱动器电路的串行器，该电路将差分信号形式的配置数据提供给可编程逻辑器件。

公开(公告)号：US07768280B1

公开(公告)日：2010-08-03

申请号：US11941034

申请日：2007-11-15

申请人： Adam J. Wright ,  Joseph W. Foerstel ,  Mark Andrew Banke ,  Ken A. Ito

发明人： Adam J. Wright ,  Joseph W. Foerstel ,  Mark Andrew Banke ,  Ken A. Ito

IPC分类号： G01R31/02

CPC分类号： G01R31/2889

摘要： A system for testing a device under test (DUT), in which electrical coupling among a module board, a low profile connector, and, a DIB is established by applying a pressure on the module board toward the DUT, is provided. The system includes a test head bracket secured inside a test head, the test head bracket includes the module board having a first section including a plurality of connectors to couple a test analyzer to the module board, a second section including a plurality of contacts pads to electrically couple the module board to the DUT, and, a flexible board to enable the first section to be placed at an angle with respect to the second section. The test head bracket also includes a module board stiffener mechanically securing the first section and the second section to the test head and the low profile connector electrically couples the module board to the DUT.

摘要翻译： 提供了一种用于测试被测器件（DUT）的系统，其中通过向模块板施加压力来建立模块板，低剖面连接器和DIB之间的电耦合。 该系统包括固定在测试头内的测试头支架，测试头托架包括模块板，模块板具有第一部分，该第一部分包括多个连接器以将测试分析仪耦合到模块板;第二部分，包括多个接触垫 将模块板电耦合到DUT，以及柔性板，以使得第一部分能够相对于第二部分以一定角度放置。 测试头支架还包括将第一部分和第二部分机械地固定到测试头的模块板加强件，并且小型连接器将模块板电耦合到DUT。

公开(公告)号：US07671579B1

公开(公告)日：2010-03-02

申请号：US11470898

申请日：2006-09-07

申请人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

发明人： Yan Chong ,  Joseph Huang ,  Chiakang Sung ,  Eric Choong-Yin Chang ,  Peter Boyle ,  Adam J. Wright

IPC分类号： G01R23/175 ,  G08B23/00

CPC分类号： H03K5/135 ,  G01R31/3016 ,  G01R31/31725 ,  G01R31/318516 ,  H03K5/14 ,  H03K5/1504

摘要： Delay associated with each of two signals along respective transmission paths is accurately measured using a delay measurement circuit that is fabricated in situ on the actual device where the circuitry for propagating the two signals is fabricated. Thus, the measured delay associated with each of the two signals is subject to the same fabrication-dependent attributes that affect the actual circuitry through which the two signals will be propagated during operation of the device. The skew between the two signals is quantified as the difference in the measured delays. Coarse and fine delay modules are defined within the transmission path of each of the two signals. Based on the measured skew between the two signals, the coarse and fine delay modules are appropriately set to compensate for the skew. The appropriately settings for the coarse and fine delay modules can be stored in non-volatile memory elements.

摘要翻译： 使用延迟测量电路精确测量与各传输路径中的两个信号中的每一个相关的延迟，该延迟测量电路在实际设备上制造，其中制造用于传播两个信号的电路。 因此，与两个信号中的每一个相关联的测量的延迟受到影响在设备操作期间两个信号将被传播的实际电路的相同制造相关属性。 两个信号之间的偏差被量化为测量延迟的差。 在两个信号中的每一个的传输路径内定义粗略和精细的延迟模块。 基于两个信号之间的测量偏差，粗调和精细延迟模块被适当地设置以补偿偏斜。 粗略和精细延迟模块的适当设置可以存储在非易失性存储器元件中。

公开(公告)号：US07546507B1

公开(公告)日：2009-06-09

申请号：US11292494

申请日：2005-12-02

申请人： Adam J. Wright ,  Daniel Reilly ,  Yoke Mooi Lee

发明人： Adam J. Wright ,  Daniel Reilly ,  Yoke Mooi Lee

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31705

摘要： A tool for testing an integrated circuit is provided. The tool includes a vector execution engine, a vector image generation engine and a vector display engine. The vector execution engine applies test patterns to the integrated circuit and captures error data being output from the test patterns. The vector image generation engine generates a file of expected output from the application of the test patterns to the integrated circuit. It should be appreciated that the generation of the vector image file occurs offline from the testing by the vector execution engine. The tool also includes a vector display engine allowing identification of vectors including error data. In one embodiment, a timestamp is associated with the vectors of the vector image file and a timestamp is associated with the vectors of the error data. A method for testing an integrated circuit and a graphical user interface are also included.

摘要翻译： 提供了一种用于测试集成电路的工具。 该工具包括矢量执行引擎，矢量图像生成引擎和矢量显示引擎。 向量执行引擎将测试模式应用于集成电路，并捕获从测试模式输出的错误数据。 矢量图像生成引擎生成从应用测试图案到集成电路的期望输出的文件。 应当理解，矢量图像文件的生成是从矢量执行引擎的测试中脱机出现的。 该工具还包括允许识别包括错误数据的向量的向量显示引擎。 在一个实施例中，时间戳与矢量图像文件的向量相关联，并且时间戳与错误数据的向量相关联。 还包括用于测试集成电路和图形用户界面的方法。

公开(公告)号：US08543876B1

公开(公告)日：2013-09-24

申请号：US12819143

申请日：2010-06-18

申请人： Adam J. Wright

发明人： Adam J. Wright

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G01R31/318544 ,  G01R31/318572

摘要： A design for test (DFT) circuitry which delivers serial data serially is disclosed. The DFT circuit has a transceiver to receive serial data and then deserialize the serial data into deserialize data. The DFT circuit also has a control logic block which receives the deserialize data and stimulates at least one test element with the test data. The test element will generate an output response from the stimulus. The DFT circuit also has an output response block which receives the output from the test element and analyses the output response. Utilizing this DFT circuitry, a high speed data delivery method can be used for testing a device-under-test (DUT). Such method could reduce test time and the test cost associated with test process.

摘要翻译： 公开了一种串行数据传输的测试（DFT）电路设计。 DFT电路具有收发器来接收串行数据，然后将串行数据反序列化为反序列化数据。 DFT电路还具有控制逻辑块，其接收反序列化数据并且用测试数据刺激至少一个测试元件。 测试元素将从刺激产生输出响应。 DFT电路还具有输出响应块，其接收来自测试元件的输出并分析输出响应。 利用该DFT电路，可以使用高速数据传输方法来测试待测器件（DUT）。 这种方法可以减少与测试过程相关的测试时间和测试成本。