发明授权
US07920410B1 Memory elements with increased write margin and soft error upset immunity
有权
存储器元件具有增加的写入裕度和软错误失真的抗扰度
- 专利标题: Memory elements with increased write margin and soft error upset immunity
- 专利标题(中): 存储器元件具有增加的写入裕度和软错误失真的抗扰度
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申请号: US12391230申请日: 2009-02-23
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公开(公告)号: US07920410B1公开(公告)日: 2011-04-05
- 发明人: Andy L. Lee , Irfan Rahim , Lu Zhou , Madhuri Mailavaram , Srinivas Perisetty
- 申请人: Andy L. Lee , Irfan Rahim , Lu Zhou , Madhuri Mailavaram , Srinivas Perisetty
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Treyz Law Group
- 代理商 G. Victor Treyz; David C. Kellogg
- 主分类号: G11C11/00
- IPC分类号: G11C11/00 ; G11C5/06
摘要:
Memory elements are provided that exhibit immunity to soft error upset events when subjected to radiation strikes such as high-energy atomic particle strikes. The memory elements may each have four inverter-like transistor pairs that form a bistable element and a pair of address transistors. There may be four nodes in the transistor each of which is associated with a respective one of the four inverter-like transistor pairs. There may be two control transistors each of which is coupled between the transistors in a respective one of the inverter-like transistor pairs. During data writing operations, the two control transistors may be turned off to temporarily decouple the transistors in two of the four inverter-like transistor pairs.
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