Invention Grant
- Patent Title: Method for etching integrated circuit structure
- Patent Title (中): 集成电路结构蚀刻方法
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Application No.: US12029834Application Date: 2008-02-12
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Publication No.: US08124537B2Publication Date: 2012-02-28
- Inventor: Chun-Hung Lee , Chia-Chi Chung , Hsin-Chih Chen , Jeff J. Xu , Neng-Kuo Chen
- Applicant: Chun-Hung Lee , Chia-Chi Chung , Hsin-Chih Chen , Jeff J. Xu , Neng-Kuo Chen
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Duane Morris LLP
- Main IPC: H01L21/311
- IPC: H01L21/311 ; H01L21/302 ; H01L21/461 ; B44C1/22 ; C03C15/00 ; C03C25/68 ; C23F1/00

Abstract:
A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.
Public/Granted literature
- US20090203217A1 NOVEL SELF-ALIGNED ETCH METHOD FOR PATTERNING SMALL CRITICAL DIMENSIONS Public/Granted day:2009-08-13
Information query
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