Invention Grant
- Patent Title: DRAM cell design with folded digitline sense amplifier
- Patent Title (中): DRAM单元设计与折叠数字线读出放大器
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Application No.: US14269944Application Date: 2014-05-05
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Publication No.: US08952437B2Publication Date: 2015-02-10
- Inventor: Fei Wang , Anton P. Eppich
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Dorsey & Whitney LLP
- Main IPC: H01L27/108
- IPC: H01L27/108 ; H01L29/76 ; H01L29/94 ; H01L31/119 ; G11C5/06 ; H01L27/02 ; G11C11/407

Abstract:
The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.
Public/Granted literature
- US20140241025A1 DRAM CELL DESIGN WITH FOLDED DIGITLINE SENSE AMPLIFIER Public/Granted day:2014-08-28
Information query
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