公开(公告)号：US20220189974A1

公开(公告)日：2022-06-16

申请号：US17654028

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541 ,  H01L21/768 ,  H01L27/11548 ,  H01L27/11575

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20220115401A1

公开(公告)日：2022-04-14

申请号：US17556704

申请日：2021-12-20

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US20200321352A1

公开(公告)日：2020-10-08

申请号：US16907967

申请日：2020-06-22

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  Fei Wang ,  Chet E. Carter ,  Ian Laboriante ,  John D. Hopkins ,  Kunal Shrotri ,  Ryan Meyer ,  Vinayak Shamanna ,  Kunal R. Parekh ,  Martin C. Roberts ,  Matthew Park

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/532

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.

公开(公告)号：US20190067306A1

公开(公告)日：2019-02-28

申请号：US15685690

申请日：2017-08-24

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L27/11551 ,  H01L27/11541

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20180114795A1

公开(公告)日：2018-04-26

申请号：US15851532

申请日：2017-12-21

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Tom J. John ,  Kunal Shrotri ,  Anish A. Khandekar ,  Aaron R. Wilson ,  John D. Hopkins ,  Derek F. Lundberg

IPC: H01L27/11582 ,  H01L21/033 ,  H01L21/311 ,  H01L29/788 ,  H01L27/11556

CPC classification number: H01L27/11582 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/31144 ,  H01L27/11556 ,  H01L29/7883

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US20130137017A1

公开(公告)日：2013-05-30

申请号：US13750963

申请日：2013-01-25

Applicant: MICRON TECHNOLOGY, INC.

Inventor： William Stanton ,  Fei Wang

IPC: G03F1/00

CPC classification number: G03F1/00 ,  G03F1/58

Abstract: Some embodiments include methods in which a mathematical representation of a photomask construction is defined, with such representation comprising a plurality of pillars that individually contain a plurality of distinct layers. Each of the layers has two or more characteristic parameters which are optimized through an optimization loop. Subsequently, specifications obtained from the optimization loop are utilized to form actual layers over an actual reticle base. Some embodiments include photomask constructions in which a radiation-patterning topography is across a reticle base, with such topography including multiple pillars that individually contain at least seven distinct layers.

Abstract translation: 一些实施例包括定义光掩模结构的数学表示的方法，其中这种表示包括单独包含多个不同层的多个柱。 每个层都有两个或更多个通过优化循环优化的特征参数。 随后，利用从优化环获得的规格在实际的掩模版基础上形成实际的层。 一些实施例包括光掩模结构，其中辐射图案化形貌横跨掩模版基底，其中这种形貌包括单独包含至少七个不同层的多个柱。

公开(公告)号：US12279423B2

公开(公告)日：2025-04-15

申请号：US17654028

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jun Fang ,  Fei Wang ,  Saniya Rathod ,  Rutuparna Narulkar ,  Matthew Park ,  Matthew J. King

IPC: H01L27/11521 ,  H01L21/768 ,  H01L27/11541 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11575 ,  H10B41/20 ,  H10B41/30 ,  H10B41/47 ,  H10B41/50 ,  H10B43/50

Abstract: A semiconductor device structure that comprises tiers of alternating dielectric levels and conductive levels and a carbon-doped silicon nitride over the tiers of the staircase structure. The carbon-doped silicon nitride excludes silicon carbon nitride. A method of forming the semiconductor device structure comprises forming stairs in a staircase structure comprising alternating dielectric levels and conductive levels. A carbon-doped silicon nitride is formed over the stairs, an oxide material is formed over the carbon-doped silicon nitride, and openings are formed in the oxide material. The openings extend to the carbon-doped silicon nitride. The carbon-doped silicon nitride is removed to extend the openings into the conductive levels of the staircase structure. Additional methods are disclosed.

公开(公告)号：US20190312056A1

公开(公告)日：2019-10-10

申请号：US16435280

申请日：2019-06-07

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Tom J. John ,  Kunal Shrotri ,  Anish A. Khandekar ,  Aaron R. Wilson ,  John D. Hopkins ,  Derek F. Lundberg

IPC: H01L27/11582 ,  H01L21/033 ,  H01L29/788 ,  H01L27/11556 ,  H01L21/311

Abstract: A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

公开(公告)号：US09128383B2

公开(公告)日：2015-09-08

申请号：US14274455

申请日：2014-05-09

Applicant: Micron Technology, Inc.

Inventor： Anton P. Eppich ,  Fei Wang

IPC: G03B27/42 ,  G03F1/00 ,  G03F1/38 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03B27/42 ,  G03F7/70058 ,  G03F7/70283 ,  G03F7/70433

Abstract: Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask includes an optically transmissive substrate having a sub-resolution assist device that further includes a first optical attenuation region and a spaced-apart second optical attenuation region, and an optically transmissive phase adjustment region interposed between the first optical attenuation region and the second optical attenuation region, the phase adjustment region being configured to change a phase of incident illumination radiation by altering an optical property of the substrate.

Abstract translation: 公开了利用次分解辅助装置的光刻设备，系统和方法。 在各种实施例中，成像掩模包括具有副分辨率辅助装置的光学透射基板，其还包括第一光学衰减区域和间隔开的第二光学衰减区域，以及光学透射相位调整区域，介于第一光学 衰减区域和第二光衰减区域，所述相位调整区域被配置为通过改变所述衬底的光学特性来改变入射照射辐射的相位。

公开(公告)号：US08952437B2

公开(公告)日：2015-02-10

申请号：US14269944

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Anton P. Eppich

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  G11C5/06 ,  H01L27/02 ,  G11C11/407

CPC classification number: G11C5/063 ,  G11C11/407 ,  H01L27/0207 ,  H01L27/10891

Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

Abstract translation: 本发明一般涉及具有折叠数字线读出放大器的DRAM单元设计。 在一个说明性实施例中，公开了具有多个有效尺寸为6F2的多个存储单元的存储器阵列，其具有多个双位有源区域，每个有源区域具有基本上纵向的轴线，并且多个数字线路布置在 折叠数字线结构，其中有源区域被定位成使得有源区域的纵向轴线相对于数字线的中心线成一定角度。