公开(公告)号：US12114489B2

公开(公告)日：2024-10-08

申请号：US17540589

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： Anton P. Eppich

IPC: G11C7/00 ,  G11C5/06 ,  G11C11/4091 ,  H10B12/00

CPC classification number: H10B12/50 ,  G11C5/063 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods for vertical access line in a folded digitline sense amplifier. An example apparatus includes an array of memory cells. The memory cells form active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region. A pair of adjacent memory cells can share a digitline contact at the second source/drain region. A storage node contact can be coupled to respective first source/drain regions and each gate can be connected to vertically oriented access lines formed on opposing side of a depletion region to each access device. An insulator material can be patterned between adjacent digitlines to isolate adjacent memory cells.

公开(公告)号：US11264320B1

公开(公告)日：2022-03-01

申请号：US17090764

申请日：2020-11-05

Applicant: Micron Technology, Inc.

Inventor： Anton P. Eppich

IPC: H01L23/522 ,  H01L27/108 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4097 ,  G11C11/4099

Abstract: Some embodiments include an integrated assembly having a set of true digit-lines and a set of complementary digit-lines. Each of the complementary digit-lines is comparatively coupled with an associated one of the true digit-lines. A semiconductor substrate is under the true digit-lines. The semiconductor substrate includes semiconductor features which project upwardly from a semiconductor base and which extend along a first direction. Each of the semiconductor features has opposing sidewalls. First source/drain regions are within the semiconductor features and second source/drain regions are within the semiconductor base. The true digit-lines are coupled with the first source/drain regions. Wordlines are along the opposing sidewalls and include gating regions which gatedly couple the first source/drain regions with the second source/drain regions. Storage-elements are coupled with the second source/drain regions. In some embodiments, memory may utilize a 4F2 layout.

公开(公告)号：US20140241025A1

公开(公告)日：2014-08-28

申请号：US14269944

申请日：2014-05-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： FEI WANG ,  Anton P. Eppich

IPC: G11C5/06 ,  G11C11/407

CPC classification number: G11C5/063 ,  G11C11/407 ,  H01L27/0207 ,  H01L27/10891

Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

Abstract translation: 本发明一般涉及具有折叠数字线读出放大器的DRAM单元设计。 在一个说明性实施例中，公开了具有多个有效尺寸为6F2的多个存储单元的存储器阵列，其具有多个双位有源区域，每个有源区域具有基本上纵向的轴线，并且多个数字线路布置在 折叠数字线结构，其中有源区域被定位成使得有源区域的纵向轴线相对于数字线的中心线成一定角度。

公开(公告)号：US20230395529A1

公开(公告)日：2023-12-07

申请号：US17860027

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Anton P. Eppich ,  Shruti Jain

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L27/11556 ,  H01L27/11582

Abstract: A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first polygon shape having at least six sides in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.

公开(公告)号：US20230180467A1

公开(公告)日：2023-06-08

申请号：US17540589

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： Anton P. Eppich

IPC: H01L27/108 ,  G11C11/4091 ,  G11C5/06

CPC classification number: H01L27/10897 ,  G11C5/063 ,  G11C11/4091

Abstract: The present disclosure includes apparatuses and methods for vertical access line in a folded digitline sense amplifier. An example apparatus includes an array of memory cells. The memory cells form active areas having adjacent access devices, each access device having a first source/drain region and a second source/drain region separated by a channel region and a gate opposing the channel region. A pair of adjacent memory cells can share a digitline contact at the second source/drain region. A storage node contact can be coupled to respective first source/drain regions and each gate can be connected to vertically oriented access lines formed on opposing side of a depletion region to each access device. An insulator material can be patterned between adjacent digitlines to isolate adjacent memory cells.

公开(公告)号：US09128383B2

公开(公告)日：2015-09-08

申请号：US14274455

申请日：2014-05-09

Applicant: Micron Technology, Inc.

Inventor： Anton P. Eppich ,  Fei Wang

IPC: G03B27/42 ,  G03F1/00 ,  G03F1/38 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03B27/42 ,  G03F7/70058 ,  G03F7/70283 ,  G03F7/70433

Abstract: Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask includes an optically transmissive substrate having a sub-resolution assist device that further includes a first optical attenuation region and a spaced-apart second optical attenuation region, and an optically transmissive phase adjustment region interposed between the first optical attenuation region and the second optical attenuation region, the phase adjustment region being configured to change a phase of incident illumination radiation by altering an optical property of the substrate.

Abstract translation: 公开了利用次分解辅助装置的光刻设备，系统和方法。 在各种实施例中，成像掩模包括具有副分辨率辅助装置的光学透射基板，其还包括第一光学衰减区域和间隔开的第二光学衰减区域，以及光学透射相位调整区域，介于第一光学 衰减区域和第二光衰减区域，所述相位调整区域被配置为通过改变所述衬底的光学特性来改变入射照射辐射的相位。

公开(公告)号：US08952437B2

公开(公告)日：2015-02-10

申请号：US14269944

申请日：2014-05-05

Applicant: Micron Technology, Inc.

Inventor： Fei Wang ,  Anton P. Eppich

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  G11C5/06 ,  H01L27/02 ,  G11C11/407

CPC classification number: G11C5/063 ,  G11C11/407 ,  H01L27/0207 ,  H01L27/10891

Abstract: The present invention is generally directed to a DRAM cell design with folded digitline sense amplifier. In one illustrative embodiment, a memory array having a plurality of memory cells having an effective size of 6F2 is disclosed which has a plurality of dual bit active areas, each of the active areas having a substantially longitudinal axis, and a plurality of digitlines arranged in a folded digitline architecture, wherein the active areas are positioned such that the longitudinal axis of the active areas is oriented at an angle with respect to a centerline of the digitlines.

Abstract translation: 本发明一般涉及具有折叠数字线读出放大器的DRAM单元设计。 在一个说明性实施例中，公开了具有多个有效尺寸为6F2的多个存储单元的存储器阵列，其具有多个双位有源区域，每个有源区域具有基本上纵向的轴线，并且多个数字线路布置在 折叠数字线结构，其中有源区域被定位成使得有源区域的纵向轴线相对于数字线的中心线成一定角度。

公开(公告)号：US20230395528A1

公开(公告)日：2023-12-07

申请号：US17860021

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Shruti Jain ,  Anton P. Eppich

IPC: H01L23/00 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/562 ,  H01L27/11582 ,  H01L27/11556

Abstract: A three-dimensional (3D) memory device including a stack of alternating supporting lattice layers and dielectric layers on a substrate, a plurality of memory pillars vertically penetrating the stack, each of the plurality of memory pillars including a plurality of vertically connected replacement gate (RG) memory cells that correspond to the supporting lattice layers, each of the memory pillars having a first square peripheral shape in a horizontal plane parallel to the supporting lattice layers, and a plurality of supporting buttress (SBT) pillars exclusive of any memory cells that are located at outside ends of the plurality of memory pillars and that vertically penetrate the stack, wherein the plurality of memory pillars and the plurality of SBT pillars are laterally connected by the supporting lattice layers.

公开(公告)号：US20140248554A1

公开(公告)日：2014-09-04

申请号：US14274455

申请日：2014-05-09

Applicant: Micron Technology, Inc.

Inventor： Anton P. Eppich ,  Fei Wang

IPC: G03F1/38 ,  G03F7/20

CPC classification number: G03F1/38 ,  G03B27/42 ,  G03F7/70058 ,  G03F7/70283 ,  G03F7/70433

Abstract: Photolithographic apparatus, systems, and methods that make use of sub-resolution assist devices are disclosed. In the various embodiments, an imaging mask includes an optically transmissive substrate having a sub-resolution assist device that further includes a first optical attenuation region and a spaced-apart second optical attenuation region, and an optically transmissive phase adjustment region interposed between the first optical attenuation region and the second optical attenuation region, the phase adjustment region being configured to change a phase of incident illumination radiation by altering an optical property of the substrate.

Abstract translation: 公开了利用次分解辅助装置的光刻设备，系统和方法。 在各种实施例中，成像掩模包括具有副分辨率辅助装置的光学透射基板，其还包括第一光学衰减区域和间隔开的第二光学衰减区域，以及光学透射相位调整区域，介于第一光学 衰减区域和第二光衰减区域，所述相位调整区域被配置为通过改变所述衬底的光学特性来改变入射照射辐射的相位。