Invention Grant
US08966299B2 Optimizing power usage by factoring processor architectural events to PMU
有权
通过将处理器架构事件分解为PMU来优化功耗
- Patent Title: Optimizing power usage by factoring processor architectural events to PMU
- Patent Title (中): 通过将处理器架构事件分解为PMU来优化功耗
-
Application No.: US14182385Application Date: 2014-02-18
-
Publication No.: US08966299B2Publication Date: 2015-02-24
- Inventor: Yen-Cheng Liu , P Keong Or , Krishnakanth Sistla , Ganapati Srinivasa
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/26
- IPC: G06F1/26 ; G06F1/22 ; G06F1/32 ; G06F1/20
Abstract:
A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
Public/Granted literature
- US20140164799A1 OPTIMIZING POWER USAGE BY FACTORING PROCESSOR ARCHITECTURAL EVENTS TO PMU Public/Granted day:2014-06-12
Information query
