Invention Grant
- Patent Title: Wafer-to-wafer stack with supporting post
- Patent Title (中): 具有支撑柱的晶圆到晶片堆叠
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Application No.: US13774939Application Date: 2013-02-22
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Publication No.: US09111774B2Publication Date: 2015-08-18
- Inventor: Chi-Shih Chang , Ra-Min Tain , Shyi-Ching Liau , Wei-Chung Lo , Rong-Shen Lee
- Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Applicant Address: TW Hsinchu
- Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Current Assignee Address: TW Hsinchu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Priority: TW94137522A 20051026
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L25/065 ; H01L23/498 ; H01L23/48 ; H01L23/00 ; H01L23/552 ; H01L23/60 ; H01L23/64
Abstract:
A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.
Public/Granted literature
- US20130161829A1 WAFER-TO-WAFER STACK WITH SUPPORTING POST Public/Granted day:2013-06-27
Information query
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