公开(公告)号：US09111774B2

公开(公告)日：2015-08-18

申请号：US13774939

申请日：2013-02-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L23/552 ,  H01L23/60 ,  H01L23/64

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L23/642 ,  H01L24/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

Abstract: A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.

Abstract translation: 晶片堆叠包括：第一晶片，具有第一基板和至少在其中具有芯片的第一器件层; 具有设置在所述第一晶片上方的第二基板的第二晶片; 以及至少第一金属柱，其存在于所述第一器件层中，并且布置在所述第一和第二基板之间，而不与所述芯片电连接。