公开(公告)号：US20130171747A1

公开(公告)日：2013-07-04

申请号：US13769824

申请日：2013-02-19

Applicant: Industrial Technology Research Institute

Inventor： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

IPC: H01L21/66

CPC classification number: H01L22/12 ,  G01N19/04 ,  H01L2224/16

Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

Abstract translation: 提供了半导体器件和机械完整性测试装置的制造方法和测试方法。 一种物体包括晶片，绝缘层和多个导电柱。 晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。 绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。 执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。 在机械完整性测试中，在第一盲孔中的导电柱被限定之后，芯片区域中的导电柱电连接到元件。

公开(公告)号：US09111774B2

公开(公告)日：2015-08-18

申请号：US13774939

申请日：2013-02-22

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Chi-Shih Chang ,  Ra-Min Tain ,  Shyi-Ching Liau ,  Wei-Chung Lo ,  Rong-Shen Lee

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/498 ,  H01L23/48 ,  H01L23/00 ,  H01L23/552 ,  H01L23/60 ,  H01L23/64

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/552 ,  H01L23/562 ,  H01L23/60 ,  H01L23/642 ,  H01L24/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/351 ,  H01L2924/00

Abstract: A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.

Abstract translation: 晶片堆叠包括：第一晶片，具有第一基板和至少在其中具有芯片的第一器件层; 具有设置在所述第一晶片上方的第二基板的第二晶片; 以及至少第一金属柱，其存在于所述第一器件层中，并且布置在所述第一和第二基板之间，而不与所述芯片电连接。

公开(公告)号：US08673658B2

公开(公告)日：2014-03-18

申请号：US13769824

申请日：2013-02-19

Applicant: Industrial Technology Research Institute

Inventor： Ming-Che Hsieh ,  John H. Lau ,  Ra-Min Tain

IPC: H01L21/12

CPC classification number: H01L22/12 ,  G01N19/04 ,  H01L2224/16

Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

Abstract translation: 提供了半导体器件和机械完整性测试装置的制造方法和测试方法。 一种物体包括晶片，绝缘层和多个导电柱。 晶片的表面在芯片区域外部具有多个第一盲孔和芯片区域内的多个第二盲孔。 绝缘层位于导电柱和第一盲孔的壁之间以及导电柱和第二盲孔的壁之间。 执行机械完整性测试以测试绝缘层，导电柱和第一盲孔的壁之间的结合强度。 在机械完整性测试中，在第一盲孔中的导电柱合格之后，芯片区域中的导电柱电连接到元件。

公开(公告)号：US20130234325A1

公开(公告)日：2013-09-12

申请号：US13873249

申请日：2013-04-30

Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE

Inventor： Ming-Ji Dai ,  Ra-Min Tain ,  Chun-Hsien Chien ,  Heng-Chieh Chien ,  Sheng-Tsai Wu

IPC: H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/11009 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16225 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/1421 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/3511 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2224/05552 ,  H01L2924/00

Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Abstract translation: 通过将高导热性和低热膨胀系数的颗粒作为复合材料添加到铜中，并将复合材料填充到通孔中，热膨胀系数与贯穿硅通孔的应力的失配是 降低了通硅通孔的导热性。