Invention Grant
- Patent Title: Method and apparatus for reducing erase disturb of memory by using recovery bias
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Application No.: US14532610Application Date: 2014-11-04
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Publication No.: US09245644B2Publication Date: 2016-01-26
- Inventor: Chun-Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
- Applicant: Macronix International Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Macronix International Co., Ltd
- Current Assignee: Macronix International Co., Ltd
- Current Assignee Address: TW Hsinchu
- Agency: Haynes Beffel & Wolfeld LLP
- Agent Kenta Suzue
- Main IPC: G11C11/34
- IPC: G11C11/34 ; G11C16/34 ; G11C16/14

Abstract:
A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
Public/Granted literature
- US20150055412A1 METHOD AND APPARATUS FOR REDUCING ERASE DISTURB OF MEMORY BY USING RECOVERY BIAS Public/Granted day:2015-02-26
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