公开(公告)号：US09245644B2

公开(公告)日：2016-01-26

申请号：US14532610

申请日：2014-11-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Long Chang ,  Ken-Hui Chen

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/14

CPC classification number: G11C16/3431 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/344

Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.

公开(公告)号：US20150055412A1

公开(公告)日：2015-02-26

申请号：US14532610

申请日：2014-11-04

Applicant: Macronix International Co., Ltd.

Inventor： Chun-Hsiung Hung ,  Bo-Chang Wu ,  Kuen-Lung Chang ,  Ken-Hui Chen

IPC: G11C16/34

CPC classification number: G11C16/3431 ,  G11C16/14 ,  G11C16/3418 ,  G11C16/344

Abstract: A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.

Abstract translation: 非易失性存储器阵列被分成多个存储器组。 非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。 控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。 通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。